Browsing by Author "Lee, S. H."

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Electrical Performances and Structural Designs of Copper Bonding in Wafer-Level Three-Dimensional Integration
(2011-06-01)
Chen, K. N.
;
Young, A. M.
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Lee, S. H.
;
Lu, J. -Q.
;
電子工程學系及電子研究所
The integrity of bonded Cu interconnects in wafer-level three-dimensional integration has been investigated as the function of pattern size and density, as well as bonding process parameter. The desired pattern density coupled with the application of bonding process profile we developed gives optimal yield and alignment accuracy, and provides excellent electrical connectivity and contact resistance through the entire wafer. This result is a key milestone in establishing the manufacturability of Cu-based interconnections for 3D integration technology.
Fabrication of Nano-Scale Cu Bond Pads with Seal Design in 3D Integration Applications
(2011-04-01)
Chen, K. N.
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Tsang, C. K.
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Wu, W. W.
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Lee, S. H.
;
Lu, J. Q.
A method to fabricate nano-scale Cu bond pads for improving bonding quality in 3D integration applications is reported. The effect of Cu bonding quality on inter-level via structural reliability for 3D integration applications is investigated. We developed a Cu nano-scale-height bond pad structure and fabrication process for improved bonding quality by recessing oxides using a combination of SiO(2) CMP process and dilute HF wet etching. In addition, in order to achieve improved wafer-level bonding, we introduced a seal design concept that prevents corrosion and provides extra mechanical support. Demonstrations of these concepts and processes provide the feasibility of reliable nano-scale 3D integration applications.