Browsing by Author "Lee, Shen-Yang"

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Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs With MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs
(2020-02-01)
Lee, Shen-Yang
;
Chen, Han-Wei
;
Shen, Chiuan-Huei
;
Kuo, Po-Yi
;
Chung, Chun-Chih
In this article, we successfully fabricated nanowire (NW) negative capacitance (NC)-related ferroelectric FETs (FE-FETs) with two structures: trigate (TG) and gate-all-around (GAA). Planar capacitors with a metal-FE-metal (MFM) structure were investigated first. Post-metal annealing (PMA) at 700 resulted in the best ferroelectricity. This condition was considerably different from that of directly stacking onto NWs because of the difference in size and curvature between planar and TG or GAA structures. Because of the addition of an underlying ZrO2 seed layer, Hf ZrxO2 in the gate-stack has been crystallized before the PMA process. In addition, two different gate-stack configurations, MFM-insulator-semiconductor (MFMIS) and metal-FE-insulator-semiconductor (MFIS), were investigated for the GAA structure. We determined that MFMIS displayed considerably more favorable subthreshold behavior and ON-state current compared with MFIS. NC-related phenomena, such as negative drain-induced barrier lowering and negative differential resistance, were observed.
Experimental Demonstration of Performance Enhancement of MFMIS and MFIS for 5-nm x 12.5-nm Poly-Si Nanowire Gate-All-Around Negative Capacitance FETs Featuring Seed-Layer and PMA-Free Process
(2019-01-01)
Lee, Shen-Yang
;
Chen, Han-Wei
;
Shen, Chiuan-Huei
;
Kuo, Po-Yi
;
Chung, Chun-Chih
We have experimentally demonstrated fully suspended nanowire ( NW) gate-all-around (GAA) negative-capacitance (NC) field-effect transistors (FETs) with ultrasmall channel dimensions (5-nm x 12.5-nm); they exhibit a remarkable I-on-I-off ratio of over 10(10). This work, for the first time, experimentally studies and compares the structures of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS) NCFETs. The GAA with the MFMIS structure has a higher on-state current owing to the metallic equal-potential layer and superior S.S.(min) of 39.22 mV/decade. A ZrO2 seed-layer is inserted under Hf Zr1-x O-x (HZO) to improve the ferroelectric crystallinity. Consequently, post-metal annealing (PMA), the conventional crystallization annealing step, can be omitted in the presence of o-phase. The gate current (I-G) is monitored to verify the multi-domain HZO. A negative DIBL of -160 mV/V is observed because of the strong NC effect corresponding to previous simulated results.
Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process
(2019-11-01)
Lee, Shen-Yang
;
Chen, Han-Wei
;
Shen, Chiuan-Huei
;
Kuo, Po-Yi
;
Chung, Chun-Chih
For the first time, two-layer stacked nanowire gate-all-around (GAA) negative capacitance (NC) field-effect transistors (FETs) with an ultrasmall poly-Si channel that has a size of $5.3\times9$ nm(2) and a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) are experimentally demonstrated. FETs exhibit a remarkable I-on-I-off ratio of more than 10(8). We demonstrated stacked channels, double layers, GAA NC-FET with a threshold voltage ( ${V}_{\textit {TH}}$ ) of 0.61 V, and a superior subthreshold behavior with an average and minimum sub- ${V}_{\textit {TH}}$ slope of 43.85 and 26.84 mV/dec, respectively. An additional ZrO2 seed layer was inserted under the Hf $_{{1-}{x}}$ ZrxO2 layer to improve ferroelectric crystallinity. Thus, the conventional crystallization annealing step can be omitted due to the presence of the orthorhombic phase ( ${o}$ -phase) before further post-metal annealing (PMA).
Nitride Induced Stress Affecting Crystallinity of Sidewall Damascene Gate-All-Around Nanowire Poly-Si FETs
(2020-01-01)
Shen, Chuan-Hui
;
Chen, Wei-Yen
;
Lee, Shen-Yang
;
Ku, Po-Yi
;
Chao, Tien-Sheng
In this article, poly-Si gate-all-around (GAA) field effect transistors (FETs) using sidewall damascene method are successfully demonstrated. By manipulating the stress which is imposed by nitride layer, the crystallinity of poly-Si channels can be modified easily by changing the thickness of nitride layer. The better crystallinity of the devices with 60 & x00A0;nm top nitride is attributed to larger average grain size and fewer defects, leading to higher field-effect carrier mobility compared to 40 and 80 & x00A0;nm top nitride layer devices. Both n-type and p-type devices exhibit superior electrical characteristics including higher on-state current of 40 & x00A0;& x03BC;A & x002F;& x03BC;m (n-type) and 26 & x00A0;& x03BC;A & x002F;& x03BC;m (p-type), steep subthreshold swing of 82 & x00A0;mV & x002F;dec. (n-type) and 104 & x00A0;mV & x002F;dec. (p-type), an extremely low drain-induced barrier lowering (DIBL) of 4.6 & x00A0;mV & x002F;V (n-type) and 16.6 & x00A0;mV & x002F;V (p-type), and high I_on& x002F;I_off current ratio larger than seven orders of magnitude. The thermal stability and gate stress reliability measurement of sidewall damascene GAA nanowire poly-Si devices were also investigated. With better crystallinity, electrical characteristics of GAA nanowire poly-Si devices degrade less under same elevated temperature condition. Devices characteristics remain unchanged after long gate stress time. This simple fabrication process makes it a potential candidate for future three-dimensional integrated-circuit (3D-IC) and low-cost Internet of Things (IoTs) applications.