Browsing by Author "Lee, Shou-Chung"

Now showing 1 - 4 of 4

Exploring Location-Related Data on Smart Phones for Activity Inference
(2014-01-01)
Ruan, Xiao-Wen
;
Lee, Shou-Chung
;
Peng, Wen-Chih
;
資訊工程學系
;
Department of Computer Science
In this paper, we propose a framework to infer different people\'s activity from the view of both the geographical habit and temporal habit of user. Such a personal activity inference framework is a crucial prerequisite for intelligent user experience, and power management of smart phones. By analyzing the real activity log data, we extract 3 kinds of features: 1) The geographical feature captures the user\'s activity preference of places; 2) The temporal feature records the routine habit of user\'s activity; 3) The semantic feature obtained from location-based social network can be used as an activity reference of public opinion for each location. Finally, we hybrid the features to build a Semantic-based Activity Inference Model (SAIM). To evaluate our proposed framework SAIM, we compared it with the state-of-art methods over a real dataset. The experimental results show that our framework could accurately inference user\'s activity and each feature of the three has different inferring ability for different user.
FUNDAMENTAL UNDERSTANDING OF POROUS LOW-K DIELECTRIC BREAKDOWN
(2009)
Lee, Shou-Chung
;
Oates, A. S.
;
Chang, Kow-Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We investigate the impact of porosity on the reliability of low-k dielectrics. We show that electric field enhancement around pores occurs and is significantly increased by Cu interaction, suggesting a new potential mechanism for breakdown of dielectrics at stress conditions. We develop of an analytic model to predict failure distribution parameters as a function of porosity and show that the model is in good agreement with measurements for porosity in the range of 5% to 40%. We explain why the field acceleration factor 7 is a constant for all silica-based material according to percolation theory. We propose that the percolation path difference between high field and low field would make the field dependence on failure time become non-linear.
Geometric Variability of Nanoscale Interconnects and Its Impact on the Time-Dependent Breakdown of Cu/Low-k Dielectrics
(2010-09-01)
Lee, Shou-Chung
;
Oates, Anthony S.
;
Chang, Kow-Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Line edge roughness (LER) and via-line misalignment strongly impact the time-dependent breakdown of the low-k dielectrics used in nanometer IC technologies. In this paper, we investigate, theoretically and experimentally, the impact of the variability of geometry on breakdown. By considering the statistical distribution of thickness between adjacent conductors exhibiting LER, we show that the breakdown location is a function of voltage and occurs at the minimum dielectric thickness at high voltage, but moves to the median thickness at the low voltages. Using these concepts, we show that LER modifies the functional form of failure distributions, and leads to a systematic change in the Weibull beta with voltage. Accurate reliability analysis requires new reliability extrapolation methodologies to account for these effects. We show that the minimum dielectric thickness present on a test structure or on a circuit is readily determined from routine measurements of dielectric thickness between metal lines. We verify theoretical predictions using measurements of failure distributions of both via and line test structures. Finally, we have shown that LER can significantly modify the apparent field dependence of the failure time, leading to ambiguity in the interpretation of the experimentally determined field dependence.
Limitation of low-k reliability due to dielectric breakdown at vias
(2008)
Lee, Shou-Chung
;
Oates, A. S.
;
Chang, Kow Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We investigate dielectric reliability associated with vias in low-k dielectric interconnects. We show that the failure mechanism of vias is identical to that of damascene lines, and occurs at the interface between the low-k and Cu-capping layers. We develop a model to accurately simulate failure distributions of via and line-only structures based on the assumption that the minimum dielectric space (highest local field) determines failure times. Via structures ultimately limit dielectric reliability of circuits because of the space reduction associated with via overlay tolerance between metal levels. We compare voltage ramp and constant voltage testing techniques and demonstrate their equivalence for via-related dielectric reliability estimation.