Browsing by Author "Lee, T. L."

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A novel technique to fabricate 28 nm p-MOSFETs possessing gate oxide integrity on an embedded SiGe channel without silicon surface passivation
(2012-12-12)
Yu, M. H.
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Liao, M. H.
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Huang, T. C.
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Wang, L. T.
;
Lee, T. L.
A novel technique to create a suspending stacked gate oxide and subsequently to fill in an embedded SiGe channel (ESC) between the gate oxide and the underlying silicon substrate is proposed for the first time to fabricate 28 nm p-metal-oxide-semiconductor field-effect transistors (p-MOSFET). Without Si surface passivation on the ESC, such an ESC structure could achieve a p-FET transconductance (G(m)) gain of 26% higher and a better I-on-I-off performance gain of 8% than that of conventional strained Si p-FETs with the source/drain (S/D) SiGe. Better S/D resistance (R-sd) in the resistance versus gate length plot and improved swing slope of the I-d-V-gs plot indicates higher mobility in the ESC devices. Moreover, the off-state gate current of the ESC structure is also comparable to the conventional ones. From the x-ray photoelectron spectrum analysis, only the Si-O bonding, and no Ge-O bonding at the SiGe/SiO2 interface could account for this superior gate oxide integrity for the ESC and strained Si structure. Therefore, such a novel technique with an ESC structure is very promising for the 28 nm p-MOSFET devices era.
Effect of gate sinking on the device performance, of the InGaP/AlGaAs/InGaAs enhancement-mode PHEMT
(2007-02-01)
Chu, L. H.
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Chang, E. Y.
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Chang, L.
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Wu, Y. H.
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Chen, S. H.
An enhancement-mode InGaP/AlGaAs/InGaAs pseudomorphic high-electron mobility transistor using platinum (Pt) as the Schottky contact metal was investigated for the first time. Following the Pt/Ti/Pt/Au gate metal deposition, the devices were thermally annealed at 325 degrees C for gate sinking. After the annealing, the device showed a positive threshold voltage (V-th) shift from 0.17 to 0.41 V and a very low drain leakage current from 1.56 to 0.16 mu A/mm. These improvements are attributed to the Schottky barrier height increase and the decrease of the gate-to-channel distance as Pt sinks into the InGaP Schottky layer during gate-sinking process. The shift in the V-th was very uniform across a 4-in wafer and was reproducible from wafer to wafer. The device also showed excellent RF power performance after the gate-sinking process.
Relaxation-free strained SiGe with super anneal for 32nm high performance PMOS and beyond
(2006)
Yu, Ming H.
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Li, J. H.
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Lin, H. H.
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Chen, C. H.
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Ku, K. C.
The interaction of epitaxially strained SiGe and super annealing or millisecond anneal in high performance PFET fabrication was, for the first time, systematically investigated. When super annealing was applied, the quality of SiGe/Si interface, affected by subsequent ion implantation and post-SiGe thermal treatment, played an important role in SiGe strain relaxation incurring channel stress loss and defect injection to Si substrate resulting in high junction leakage. Defect injection mechanism was proposed to explain the defect formation in Si substrate. The new processing scheme, which preserved SiGe as relaxation-free and avoided defect injection, was developed and for 32nm technology. The device performance gain with 10% Id,sat increment resulting from fully strained SiGe was achieved.
The Dependence of the Performance of Strained NMOSFETs on Channel Width
(2009-11-01)
Yeh, Lingyen
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Liao, Ming Han
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Chen, Chun Heng
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Wu, Jun
;
Lee, Joseph Ya-Min
The dependence of the performance of strained NMOSFETs on channel width was investigated. When the channel width was varied, the stress in the channel varied accordingly. This changed the electron effective mass and, consequently, the ON-state current I(on). By shrinking the channel width of a strained NMOSFET from 1 to 0.1 mu m and by keeping the channel length at 55 nm, the ON-state drain current per unit channel width was enhanced by 22%. The gate leakage current was also affected by the stress in the channel, which can be explained by the increase in hole barrier height at the Si/SiO(2) interface. Furthermore, when the film stress was increased by 1 GPa, the gate leakage current density J(g) of a strained NMOSFET with a channel width of 0.1 mu m and a length of 55 nm under a negative bias -3 V was reduced by 63%.
The Strained-SiGe Relaxation Induced Underlying Si Defects Following the Millisecond Annealing for the 32 nm PMOSFETs
(2012)
Yu, M. H.
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Wang, L. T.
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Huang, T. C.
;
Lee, T. L.
;
Cheng, H. C.
The formation of the induced defects in the underlying Si substrate from the interaction of the partly relaxed source/drain strained-SiGe layer and subsequent millisecond annealing (MSA) have been systematically explored. It could be found that implantation in the shallower region of the strained-SiGe layer did not form defects in the underlying Si because the remaining strained-SiGe layer was sufficiently thick to resist wafer bending in response to the MSA thermal stress. However, deeper medium-level implantation indeed destroyed the part of the pseudomorphic strained-SiGe and the remaining strained-SiGe was too thin to withstand a significantly compressive stress induced by MSA surface heating and larger coefficient of thermal expansion (CTE) for SiGe than it for Si. Then brittle silicon substrate suffered a great tensile stress to generate numerous defects into plastic deformation. During MSA cooling, the over-bending of the surface SiGe layer contracted more than Si substrate and further results in highly tensile bending. Consequently, high defect density in the underlying Si results in high junction leakage and wafer bending leads to photolithographic limitation. A new approach for modifying the implantation conditions was developed to achieve a relaxation-less strained-SiGe layer and defect-free underlying Si substrate for the 32 nm PMOSFETs. (C) 2011 The Electrochemical Society. [DOI: 10.1149/2.017203jes] All rights reserved.