Browsing by Author "Lee, Tai-Cheng"

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Efficient Heat Dissipation of Uncooled 400-Gbps (16x25-Gbps) Optical Transceiver Employing Multimode VCSEL and PD Arrays
(2017-04-18)
Shih, Tien-Tsorng
;
Chi, Yu-Chieh
;
Wang, Ruei-Nian
;
Wu, Chao-Hsin
;
Huang, Jian-Jang
An effective heat dissipation of uncooled 400-Gbps (16x25-Gbps) form-factor pluggable (CDFP) optical transceiver module employing chip-on-board multimode 25-Gbps vertical-surface-emitting-laser (VCSEL) and 25-Gbps photodiode (PD) arrays mounted on a brass metal core embedded within a printed circuit board (PCB) is proposed and demonstrated. This new scheme of the hollow PCB filling with thermally-dissipated brass metal core was simulated and used for high temperature and long term stability operation of the proposed 400-Gbps CDFP transceiver. During one-hour testing, a red-shift of central wavelength by 0.4-nm corresponding temperature increment of 6.7 degrees C was observed with the brass core assisted cooler module. Such a temperature change was significantly lower than that of 28.3 degrees C for the optical transceiver driven with conventional circuit board. After 100-m distance transmission over a multimode fiber (OM4), the 400-Gbps CDFP transceiver exhibited dispersion penalty of 2.6-dB, power budget of >= 3-dB, link loss of <= 0.63-dB, mask margin of 20%, and bit error rate (BER) of <10(-12) with maintained stability more than one hour. The developed 400-Gbps CDFP transceiver module employing low-power consumption VCSEL and PD arrays, effective coupling lens arrays, and well thermal-dissipation brass metal core is suitable for use in the low-cost and high-performance data center applications.
Few-Mode 850-nm VCSEL Chip with Direct 16-QAM OFDM Encoding at 80-Gbit/s for 100-m OM4 MMF Link
(2017-01-01)
Kao, Hsuan-Yun
;
Tsai, Cheng-Ting
;
Pong, Chun-Yen
;
Liang, Shan-Fong
;
Weng, Zu-Kai
Chip-level direct 16-QAM OFDM encoding of a few-transverse-mode 850-nm Zn-diffused VCSEL is employed to transmit 80-Gbit/s data covering 20-GHz analog bandwidth over 100-m-long OM4 MMF with corresponding BER of 3.3x10(-3).
Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell Delay
(2019-10-01)
Lee, Tai-Cheng
;
Li, Yih-Lang
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資訊工程學系
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Department of Computer Science
Satisfying timing requirements is the most challenging phase of the modern complex system-on-chip (SOC) design. The timing closure of the static timing analysis (STA) is a necessary but time-consuming stage before tapeout. Physical design tools are normally ineffective in obtaining accurate timing estimates, so the accurate timing calculation must be conducted in the signoff level timer after each physical modification on designs. This paper proposes a way to reduce the number of iterations between the signoff timer and the physical implementation procedures. Approximate timing models for extracting the signoff timer information and the nonlinear library are used in the optimization of the timing-driven placement (TDP). The accurate estimation of net and cell delays is integrated into TDP, so the optimal positions of cell movement can be obtained. This postoptimization algorithm was entered into the benchmark of the ICCAD15 incremental timing-driven contest, and the embodiments were obtained from the top three teams. Under the same design constraints, the proposed method yielded significant improvements in all kinds of default design chip.