Browsing by Author "Lee, Wei-Li"

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Fully Depleted GeOI-Channel Junctionless pMOSFET with a Low-Resistance-Raised NiGe Alloy S/D
(2017-01-01)
Lee, Wei-Li
;
Hsu, Chung-Chun
;
Chung, Cheng-Ting
;
Lu, Yu-Hung
;
Luo, Guang-Li
We fabricated a Ge junctionless p-channel metal-oxide-semiconductor field-effect transistor (JL pMOSFET) with a raised metal source/drain (S/D) composed of a metal alloy. An ultrathin-body Ge channel was trimmed to 10 nm, which is lower than the maximum depletion width, to completely switch off the device. The fabricated Ge JL pMOSFET containing a raised Ni/NiGe S/D exhibited a high on/off current ratio (I-on/I-off) value (approximately 10(5) at V-DS =-0.1 V). The S/D series resistance of the full metal S/D structure was exactly lower than the structures of Ge/NiGe and Ge bulk S/D. Synopsys Technology Computer-Aided Design tools were used to confirm the advantages of the full metal S/D structure and demonstrate the enhancement of the S/D resistance in a device with scaled gate length. The proposed scheme is suitable for reducing the series resistance of a device with minimized dimensions. (C) 2017 The Electrochemical Society. All rights reserved.
Improving Interface State Density and Thermal Stability of High-kappa Gate Stack Through High-Vacuum Annealing on Si0.5Ge0.5
(2019-05-01)
Lee, Wei-Li
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Yu, Cheng-Yu
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Zhang, Jun-Lin
;
Luo, Guang-Li
;
Chien, Chao-Hsin
We fabricated HfO2-based gate stacks on epi-Si0.5Ge0.5 substrates and investigated the effect of thermal treatment on their structural and electrical properties at varying temperatures and pressures in oxygen ambient. The thermal treatment process led to severe degradation of interface quality as the temperature increased. Material analyses indicated that annealing in oxygen ambient resulted in oxygen diffusion from the high-k material to the SiGe surface, causing undesirable SiGe reoxidation. In high-vacuum annealing, an interface state density of approximately 1.4 x 10(11) eV(-1) cm(-2) and a thermal stability of up to 500 degrees C were achieved for the gate stack on SiGe.
Integration of Hetero-Structure Body-Tied Ge FinFET Using Retrograde-Well Implantation
(2016)
Chou, Yu-Che
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Hsu, Chung-Chun
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Chun, Cheng-Ting
;
Chou, Chen-Han
;
Tsai, Ming-Li
In this work, we investigated the influence of retrograde-well implantation on hetero-structure body-tied germanium (Ge) FinFET [1]. Using structural engineering, the retrograde well was fabricated prior to Ge epitaxy, which could avoid the activated temperature of dopant in Si substrate. With optimizing the implant condition, the p-Ge/n-Si hetero-structure junction exhibited high I-ON/I-OFF ratio and lower junction leakage (4x10(-3)mu A/cm(2)). Furthermore, we also make a comparison of planar and mesa junction structures, mesa junction exhibited lower junction leakage (6x10(-6)mu A/cm(2))as compared with the planar one mentioned before, which could be attributed to improvement in peripheral leakage due to dislocation within Ge and Si. Comparing the difference between retrograde-well and implant-free Ge FinFETs, the drain induced barrier lowering (DIBL) was considerably improved by 50 %. Our retrograde-well Ge FinFET exhibited a high I-ON/I-OFF ratio similar to 8x10(3) (I-S) than the conventional Ge FinFET (I-ON/I-OFF similar to 2x10 (3)).
Spin-Glass Transition and Giant Paramagnetism in Heavily Hole-Doped Bi2Sr2Co2Oy
(2014-02-01)
Hsu, Hung Chang
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Lee, Wei-Li
;
Lin, Jiunn-Yuan
;
Young, Ben-Li
;
Kung, Hsiang-Hsi
Hole-doped single crystals of misfit-layered cobaltate Bi2-xPbxSr2-zCo2Oy (x = 0-0.61, y = 8.28-8.62, and z = 0.01-0.22) have been successfully grown using the optical floating-zone method. Heavier hole doping has been achieved through both Pb substitution in the Bi site and the more effective Sr vacancy formation. The Co4+ : Co3+ ratio can be raised significantly from its original similar to 1 : 1 to 4.5 : 1, as confirmed by iodometric titration. A spin-glass transition temperature of T-g similar to 70K is confirmed by ac susceptibility measurement when the Co4+ : Co3+ ratio becomes higher than 2 : 1, presumably owing to the significantly increased probability of triangular geometrical frustration among antiferromagnetically coupled localized Co4+ spins.
Study of High-Ge-Content Si0.16Ge0.84 Gate Stack by Low Pressure Oxidation
(2018-01-01)
Lee, Wei-Li
;
Zhang, Jun-Lin
;
Tsai, Ming-Li
;
Wang, Shin-Yuan
;
Luo, Guang-Li
In this study, we employed low-pressure oxidation (LPO) to achieve a high-quality dielectric gate stack on high-Ge-content (HGC) Si0.16Ge0.84. According to X-ray photoelectron spectroscopy depth-profiling results, lowering the oxidation pressure can drive out-diffusion of Si atoms from the HGC SiGe surface, resulting in the suppression of GeOx formation. A nearly GeOx-free interfacial layer detected at an O-2 pressure of 0.01 torr at 600 degrees C was used. Consequently, the formation of stable SiOx resulted in the improvement of D-it and gate leakage current, which in accumulation (V-FB-1V) was also considerably reduced with an equivalent oxide thickness of 1.5 nm. Finally, by applying the LPO process and optimized process conditions, the interface trap density (D-it) was reduced to 2 x 10(12) eV(-1) cm(-2). (C) 2018 The Electrochemical Society.