Browsing by Author "Lee, Yu-Min"

Now showing 1 - 20 of 27

A Hierarchical Bin-Based Legalizer for Standard-Cell Designs with Minimal Disturbance
(2010)
Lee, Yu-Min
;
Wu, Tsung-You
;
Chiang, Po-Yi
;
交大名義發表
;
National Chiao Tung University
In this work, a hierarchical bin-based legalization approach, HiBinLegalizer, is developed to legalize standard cells with minimal movement. First, a chip is divided into several bins with equal size. Then, starting with the most crowed unlegalized bin, a merging procedure for bins is used to integrate bins into a cross-shape region or a square-shape region until the cell density in that region is less than a specific cell-density-threshold. After that, an efficient legalization method which simultaneously preserves the cell orders in each row and minimizes the weighted sum of movement distances is developed to legalize cells in that region to limit the movable scope. To improve the legalization quality, HiBinLegalizer refreshes the positions of legalized cells during legalization. The legalizing procedure is repeated until all cells are non-overlapped. Compared with the state-of-the-art method, Abacus, HiBinLegalizer can reduce the total movement of cells to be 48% in average and save the largest movement of cells to be 140% in average. Moreover, HiBinLegalizer can reduce the HPWL by 47% and obtain average 1.11 x runtime speed up.
A Multiple Supply Voltage Based Power Reduction Method in 3-D ICs Considering Process Variations and Thermal Effects
(2009)
Yu, Shih-An
;
Huang, Pei-Yu
;
Lee, Yu-Min
;
電信工程研究所
;
Institute of Communications Engineering
In this paper, a grid-based multiple supply voltage (MSV) assignment method is presented to statistically minimize the total power consumption of 3-D IC. This method consists of a statistical electro-thermal simulator to get the mean and variance of on-chip, a thermal-aware statistical static timing analysis (SSTA) to take into account the thermal effect on circuit timing, the statistical power-delay-sensitivity-slack product to be the optimization criterion, and an incremental update of statistical timing to save the runtime. The experimental results demonstrate the effectiveness of the developed methodology and indicate that the consideration of the thermal effect in the circuit simulation is imperative.
A Robust Incremental Power Grid Analyzer by Macromodeling Approach and Orthogonal Matching Pursuit
(2012)
Lee, Yi-Hsuan
;
Lee, Yu-Min
;
Cheng, Liang-Chia
;
Chang, Yen-Tang
;
交大名義發表
As VLSI techniques are getting more and more advanced, the size of the power grid network increases dramatically. Therefore, the power grid analysis becomes a challenging task during the design procedure. This work utilizes the macromodeling technique [1] and enhances the Orthogonal Matching Pursuit (OMP) based method [2] to develop an effective and robust incremental analysis method for the power grid network, MA-OMPt. Given a power grid network, MA-OMPt not only can deal with the change of its element values but also can handle the modification of its topology. The experimental results show that MA-OMPt can be an order of magnitude faster than the OMP-based method [2] which can only deal with the change of element values of the power grid. The experimental results also demonstrate that MA-OMpt can accurately and efficiently handle the modified topology of the power grid network.
A System-Level Thermal Simulator with Automatic Meshing Techniques
(2018-01-01)
Wang, Jui-Hung
;
Lee, Yu-Min
;
Hsiao, Hsuan-Hsuan
;
Cheng, Liang-Chia
;
電機工程學系
The grid structure of most numerical thermal simulators has to be designed artificially. Designers might need to try many different grid structures for getting accurate thermal profiles, and, hence, waste a great of runtime. In order to solve this problem, this work presents a system-level thermal simulator, DeNAFE, which can adaptively mesh thermal grids automatically. First, we develop and employ a fast thermal estimation engine to roughly obtain the thermal profile of the system. Then, with this thermal profile, we propose and utilize an adaptive meshing procedure to decide its grid structure and perform thermal simulation. Compared with a commercial tool, ANSYS Icepak, the experimental results show that the speedup of DeNAFE can be up to two orders of magnitude with only 6: 09% maximum error for all chips in the steady-state thermal simulation. Furthermore, the error of chips is less than 5: 25%, the error of screen/skin is less than 6: 03%, and the speedup can be over 171: 12 times in the transient simulation.
A TSV Noise-Aware 3-D Placer
(2015)
Lee, Yu-Min
;
Chen, Chun
;
Song, JiaXing
;
Pan, Kuan-Te
;
交大名義發表
In this work, a three-dimensional partitioning-based force-directed placer is developed to minimize coupling noise between through silicon vias (TSVs) in three-dimensional integrated circuits. TSV decoupling force is introduced and determined by the TSV coupling noise to separate TSVs with strong coupling noise. The experimental results indicate that TSV coupling noise can be effectively reduced by 36.3% on average with only 6.0% wirelength overhead. Besides, the developed 3-D placer shows great performance in wirelength that is competitive to a state-of-the-art 3-D placer.
An Efficient Method for Analyzing On-Chip Thermal Reliability Considering Process Variations
(2013-07-01)
Lee, Yu-Min
;
Huang, Pei-Yu
;
電機資訊學士班
;
Undergraduate Honors Program of Electrical Engineering and Computer Science
This work provides an efficient statistical electrothermal simulator for analyzing on-chip thermal reliability under process variations. Using the collocation-based statistical modeling technique, first, the statistical interpolation polynomial for on-chip temperature distribution can be obtained by performing deterministic electrothermal simulation very few times and by utilizing polynomial interpolation. After that, the proposed simulator not only provides the mean and standard deviation profiles of on-chip temperature distribution, but also innovates the concept of thermal yield profile to statistically characterize the on-chip temperature distribution more precisely, and builds an efficient technique for estimating this figure of merit. Moreover, a mixed-mesh strategy is presented to further enhance the efficiency of the developed statistical electrothermal simulator. Experimental results demonstrate that (1) the developed statistical electrothermal simulator can obtain accurate approximations with orders of magnitude speedup over the Monte Carlo method; (2) comparing with a well-known cumulative distribution function estimation method, APEX [Li et al. 2004], the developed statistical electrothermal simulator can achieve 215x speedup with better accuracy; (3) the developed mixed-mesh strategy can achieve an order of magnitude faster over our baseline algorithm and still maintain an acceptable accuracy level.
Full-Chip Thermal Analysis for the Early Design Stage via Generalized Integral Transforms
(2009-05-01)
Huang, Pei-Yu
;
Lee, Yu-Min
;
電信工程研究所
;
Institute of Communications Engineering
The capability of predicting the temperature profile is critically important for timing estimation, leakage reduction, power estimation, hotspot avoidance and reliability concerns during modern IC design. This paper presents an accurate and fast analytical full-chip thermal simulator for early-stage temperature-aware chip design. By using the generalized integral transforms (GIT), an accurate formulation is derived to estimate the temperature distribution of full-chip with a truncated set of spatial bases which only needs very small truncation points. Then, we develop a fast Fourier transform like evaluating algorithm to efficiently evaluate the derived formulation. Experimental results confirm that the proposed GIT-based analyzer can achieve an order of magnitude speedup compared with a highly efficient Green's function-based thermal simulator. Finally, we propose a 3-D IC thermal simulator and demonstrate its efficiency and accuracy.
Hierarchical power delivery network analysis using Markov chains
(2007)
Huang, Pei-Yu
;
Lin, Chih-Kang
;
Lee, Yu-Min
;
電信工程研究所
;
Institute of Communications Engineering
This paper proposes a Markov chain based hierarchical method to efficiently analyze the power delivery network. After the network being partitioned into several subnetworks, each subnetwork is transformed into a local Markov chain. Then, the connective relations between all subnetworks are modeled as a global Markov chain. Finally, those local and the global Markov chains are incorporated to build a hierarchical bipartite Markov chain engine to analyze the power delivery network. The experimental results not only demonstrate the accuracy of proposed method compared with a very accurate time domain solver [1], but also show its significant runtime improvement, over 200 times faster than the InductWise [1] and over 10 times faster than the IEKS method [2], and less memory usage.
I-LUTSim: An Iterative Look-Up Table Based Thermal Simulator for 3-D ICs
(2013-01-01)
Pan, Chi-Wen
;
Lee, Yu-Min
;
Huang, Pei-Yu
;
Yang, Chi-Ping
;
Lin, Chang-Tzu
This work presents an iterative look-up table based thermal simulator, I-LUTSim, to efficiently estimate the temperature profile of three-dimensional integrated circuits. I-LUTSim includes two stages. First, the pre-process stage constructs thermal impulse response tables. Then, the simulation stage iteratively calculates the temperature profile via the table lookup. With this two-stage scheme, the maximum absolute error of I-LUTSim is less than 0.41% compared with that of a commercial tool ANSYS. Moreover, I-LUTSim is at least an order of magnitude faster than a fast matrix solver SuperLU [1] for the full-chip temperature simulation.
InTraSim: Incremental Transient Simulation of Power Grids
(2017-12-01)
Lee, Yu-Min
;
Ho, Chia-Tung
;
電機工程學系
;
Department of Electrical and Computer Engineering
Effective transient power grid simulators are needed during design processes because a designed power grid needs to be numerously analyzed. This paper builds an efficient and reliable incremental power grid transient simulator, which we name it InTraSim, by integrating macro modeling techniques, sparse recovery mechanisms, an innovated pseudo-node value estimation method, and an initiated adaptive error control scheme. InTraSim is able to deal with not only element-value alterations of designs but also topology modifications of designs.
Learning Based Mesh Generation for Thermal Simulation in Handheld Devices with Variable Power Consumption
(2019-01-01)
Lo, Wen-Sheng
;
Chiou, Hong-Wen
;
Hsu, Shih-Chieh
;
Lee, Yu-Min
;
Cheng, Liang-Chia
This work utilizes machine learning techniques to achieve learning based mesh generation for the thermal simulator. In the learning stage, first, we generate many power value sets of application processors and apply the superposition technique to obtain the temperature raw data of material blocks. We, then, use these thermal data and several defined thermal gradient ranges to obtain different appropriate mesh-size sets of material blocks for each power value set. We construct the regressions that are capable of predicting targets as a supervised learning task, and the architecture of regression model includes seven hidden layers. After the learning stage, we integrate the learning based mesh decision engine into a developed system-level thermal simulator, which is built by the finite difference method. The experimental results show that the temperature profiles of the handheld device calculated by the developed thermal simulator with learning based mesh generation fits the results obtained by a commercial tool pretty well with less runtime usages. Moreover, the learning based mesh decision engine is much more efficient than the artificial mesh decision.
LUTSim: A Look-Up Table-Based Thermal Simulator for 3-D ICs
(2015-08-01)
Lee, Yu-Min
;
Pan, Chi-Wen
;
Huang, Pei-Yu
;
Yang, Chi-Ping
;
電機資訊學士班
To sustain Moore\'s law, three-dimensional integrated circuit (3-D IC) is a promising solution to achieve high performance and low cost targets. However, its operating temperature is higher than that of a 2-D IC because of its high power density of stacked dies and ill of heat dissipation capability. Therefore, on-chip thermal effects have become major concerns of 3-D ICs. Utilizing look-up table approach, this paper, LUTSim, provides two thermal simulation engines, I-LUTSim and S-LUTSim, to efficiently calculate the thermal profile of a 3-D IC. I-LUTSim is suitable for full-chip thermal analysis, and S-LUTSim is suited for incremental-thermal updating. With utilizing the prebuilt tables, compared with a commercial tool ANSYS, the absolute error of I-LUTSim is less than 0.29%. Moreover, with negligible loss of accuracy, I-LUTSim can be 38.8 times faster than a well-known matrix solver SuperLU for performing full-chip thermal simulation. Besides, S-LUTSim can be over 1.05 million times faster than SuperLU for adjusting the thermal profile after inserting/removing a through silicon via.
Multi-Angle Bended Heat Pipe Design Using X-Architecture Routing with Dynamic Thermal Weight on Mobile Devices
(2019-01-01)
Hsiao, Hsuan-Hsuan
;
Chiou, Hong-Wen
;
Lee, Yu-Min
;
交大名義發表
;
電信工程研究所
Heat pipe is an effective passive cooling technique for mobile devices. This work builds a multi-angle bended heat pipe thermal model and presents an X-architecture routing engine guided by developed dynamic thermal weights to construct the heat pipe path for reducing the operating temperatures of a smartphone. Compared with a commercial tool, the error of the thermal model is only 4.79%. The routing engine can efficiently reduce the operating temperatures of application processors at least 13.20% in smartphones.
NaPer: A TSV Noise-Aware Placer
(2017-05-01)
Lee, Yu-Min
;
Pan, Kuan-Te
;
Chen, Chun
;
電機工程學系
;
Department of Electrical and Computer Engineering
Through-silicon-via (TSV)-to-TSV coupling issue can degrade the signal integrity in 3-D integrated circuit designs. This paper develops a 3-D partitioning-based force-directed placer, NaPer, to reduce the total coupling noise between TSVs and alleviate the maximum coupling noise between them. We introduce two denoise forces: TSV decoupling force and TSV density force. The TSV decoupling force is determined by the coupling noise between TSVs for separating strong coupling TSVs, and the TSV density force is determined by the TSV density for evenly distributing TSVs. The experimental results show that NaPer can effectively reduce 15.0% total TSV coupling noise and 42.7% maximum TSV coupling noise on average with only 4.5% wirelength overhead. Besides, NaPer also shows great performance in wirelength that is competitive to the state-of-the-art 3-D placer.
NUMANA: A Hybrid Numerical and Analytical Thermal Simulator for 3-D ICs
(2013-01-01)
Lee, Yu-Min
;
Wu, Tsung-Heng
;
Huang, Pei-Yu
;
Yang, Chi-Ping
;
交大名義發表
By combining analytical and numerical simulation techniques, this work develops a hybrid thermal simulator, NUMANA, which can effectively deal with complicated material structures, to estimate the temperature profile of a 3-D IC. Compared with a commercial tool, ANSYS, its maximum relative error is only 1.84%. Compared with a well known linear system solver, SuperLU [1], it can achieve orders of magnitude speedup.
On-Chip Statistical Hot-Spot Estimation Using Mixed-Mesh Statistical Polynomial Expression Generating and Skew-Normal Based Moment Matching Techniques
(2012)
Huang, Pei-Yu
;
Lee, Yu-Min
;
Pan, Chi-Wen
;
電機工程學系
;
Department of Electrical and Computer Engineering
This work introduces the concept of thermal yield profile for the hot-spot identification with considering process variations and provides an efficient estimating technique for the thermal yield profile. After executing a mixed-mesh strategy for generating statistical polynomial expression of the on-chip temperature distribution, the thermal yield profile is obtained by a skew-normal based moment matching technique. Comparing with the Monte Carlo method, experimental results demonstrate that our method can efficiently and accurately estimate the thermal yield profile. With the same level of accuracy, our skew-normal based method achieves 215x speedup over the state of the art, APEX [1], for estimating the thermal yield profile. Moreover, results show that our mixed-mesh statistical polynomial expression generator achieves 130x speedup over the statistical collocation based method [2] and still accurately estimates the thermal yield profile.
Phone-nomenon: A System-Level Thermal Simulator for Handheld Devices
(2019-01-01)
Chiou, Hong-Wen
;
Lee, Yu-Min
;
Shiau, Shin-Yu
;
Pan, Chi-Wen
;
Chen, Tai-Yu
This work presents a system-level thermal simulator, Phone-nomenon, to predict the thermal behavior of smartphone. First, we study the nonlinearity of internal and external heat transfer mechanisms and propose a compact thermal model. After that, we develop an iterative framework to handle the nonlinearity. Compared with a commercial tool, ANSYS Icepak, Phonenomenon can achieve two and three orders of magnitude speedup with 3:58% maximum error and 1:72 degrees C di fference for steady-state and transient-state simulations, respectively. Meanwhile, Phone-nomenon also fits the measured data of a built thermal test vehicle pretty well.
Post-Routing Redundant Via Insertion with Wire Spreading Capability
(2009)
Lei, Cheok-Kei
;
Chiang, Po-Yi
;
Lee, Yu-Min
;
電信工程研究所
;
Institute of Communications Engineering
Redundant via insertion is a widely recommended technique to enhance the via yield and reliability. In this paper, the post-routing redundant via insertion problem is transformed to a mixed bipartite-conflict graph matching problem, and an efficient heuristic minimum weighted matching (HMWM) algorithm is presented to solve it. The developed method not only inserts redundant vias for alive vias but also protects the dead vias by utilizing the wire spreading capability- that's to say, the method shifts wires into the empty space and adds redundant vias for dead vias to further enhance the via yield. Experimental results show that the average insertion rate of alive vias is 99.54% with a short run time, and the wire spreading technique can achieve average insertion rate to be 54.41% for dead vias.
Power Delivery Network Design for Wiring and TSV Resource Minimization in TSV-Based 3-D ICs
(2013-01-01)
Wei, Shu-Han
;
Lee, Yu-Min
;
Ho, Chia-Tung
;
Sun, Chih-Ting
;
Cheng, Liang-Chia
This work presents effective techniques for minimizing wiring resources and power TSVs (PTSVs) of 3-D power delivery network design under IR drop constraints. First, a 3-D power grid topology optimization is performed to generate power grid by utilizing locally uniform and globally non-uniform power grid configurations. After that, two developed power TSV planners are executed to minimize the maximum IR drop without the full-chip power-grid analysis. Finally, the above procedures are repeatedly performed with a rescue procedure to remedy the violated constraints until the designed PDN is satisfied. To further enhance the design procedure, a partition-based design flow is proposed by dividing the entire chip into tiles, and each of them is designed independently by the proposed procedure. The experimental results demonstrate the effectiveness of the developed methodology and indicate that the consideration of partition-based strategy in the design flow is imperative.
Power Delivery Network Design for Wiring and TSV Resource Minimization in TSV-Based 3-D ICs
(2013)
Wei, Shu-Han
;
Lee, Yu-Min
;
Ho, Chia-Tung
;
Sun, Chih-Ting
;
Cheng, Liang-Chia
This work presents effective techniques for minimizing wiring resources and power TSVs (PTSVs) of 3-D power delivery network design under IR drop constraints. First, a 3-D power grid topology optimization is performed to generate power grid by utilizing locally uniform and globally non-uniform power grid configurations. After that, two developed power TSV planners are executed to minimize the maximum IR drop without the full-chip power-grid analysis. Finally, the above procedures are repeatedly performed with a rescue procedure to remedy the violated constraints until the designed PDN is satisfied. To further enhance the design procedure, a partition-based design flow is proposed by dividing the entire chip into tiles, and each of them is designed independently by the proposed procedure. The experimental results demonstrate the effectiveness of the developed methodology and indicate that the consideration of partition-based strategy in the design flow is imperative.