Browsing by Author "Lee, Yung-Yu"

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A 188-size 2.1mm(2) Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE System
(2009)
Wong, Cheng-Chi
;
Lee, Yung-Yu
;
Chang, Hsie-Chia
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a turbo decoder chip supporting all 188 block sizes in 3GPP LTE standard. The design allows 1, 2, 4, or 8 SISO decoders to concurrently process each block size, and the number of iteration can be adjusted. Moreover, a three-stage network is utilized to connect multiple memory modules and multiple SISO decoders. After fabricated in 90nm process, the 2.1mm(2) chip can achieve 129Mb/s with 219mW for the 6144-bit block after 8 iterations.
A 188-size 2.1mm(2) Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE System
(2009)
Wong, Cheng-Chi
;
Lee, Yung-Yu
;
Chang, Hsie-Chia
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a turbo decoder chip supporting all 188 block sizes in 3GPP LTE standard. The design allows 1, 2, 4, or 8 SISO decoders to concurrently process each block size, and the number of iteration can be adjusted. Moreover, a three-stage network is utilized to connect multiple memory modules and multiple SISO decoders. After fabricated in 90nm process, the 2.1mm(2) chip can achieve 129Mb/s with 219mW for the 6144-bit block after 8 iterations.
A 188-size 2.1mm(2) Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE System
(2009-01-01)
Wong, Cheng-Chi
;
Lee, Yung-Yu
;
Chang, Hsie-Chia
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a turbo decoder chip supporting all 188 block sizes in 3GPP LTE standard. The design allows 1, 2, 4, or 8 SISO decoders to concurrently process each block size, and the number of iteration can be adjusted. Moreover, a three-stage network is utilized to connect multiple memory modules and multiple SISO decoders. After fabricated in 90nm process, the 2.1mm(2) chip can achieve 129Mb/s with 219mW for the 6144-bit block after 8 iterations.