Browsing by Author "Lee, ZM"

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A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration
(2005-05-01)
Liu, HC
;
Lee, ZM
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This study presents a 15-b 40-MS/s switched-capacitor CMOS pipelined analog-to-digital converter (ADC). High resolution is achieved by using a correlation-based background calibration technique that can continuously monitor the transfer characteristics of the critical pipeline stages and correct the digital output codes accordingly. The calibration can correct errors associated with capacitor mismatches and finite opamp gains. The ADC was fabricated using a 0.25-mu m 1P5M CMOS technology. Operating at a 40-MS/s sampling rate, the ADC attains a maximum signal-to-noise-plus-distortion ratio of 73.5 dB and a maximum spurious-free-dynamic-range of 93.3 dB. The chip occupies an area of 3.8 x 3.6 mm(2), and the power consumption is 370 mW with a single 2.5-V supply.
A 15-bit 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration (vol 40, pg 1047, 2005)
(2005-11-01)
Liu, HC
;
Lee, ZM
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 15b 20MS/s CMOS pipelined ADC with digital background calibration
(2004)
Liu, HC
;
Lee, ZM
;
Wu, JT
;
交大名義發表
;
National Chiao Tung University
Digital background calibration technique for pipelined analog-to-digital converters
(2003)
Liu, HC
;
Lee, ZM
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new background calibration technique for pipelined analog-to-digital converters is proposed. By dividing the step sizes of the multiplying digital-to-analog converter (MDAC) in a pipeline stages and injecting a random signal into the MDAC, it is possible to calibrate a pipeline stage without interrupting the normal analog-to-digital operation. The calibration can eliminate the nonlinear effects due to the MDAC's gain error, input offset voltage, and output errors in the digital-to-analog conversion.