Browsing by Author "Lee, Zwei-Mei"

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A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background calibration
(2007-10-01)
Lee, Zwei-Mei
;
Wang, Cheng-Yeh
;
Wu, Jieh-Tsorng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 15-bit 125-MS/s two-channel time-interleaved pipelined ADC is fabricated in a 0.18 mu m CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. This ADC incorporates a single sample-and-hold amplifier which employs a precharged circuit configuration to mitigate performance requirements for its opamp. Digital background calibration is applied to maintain the conversion linearity of each A/D channel and also correct both gain and offset mismatches between the two channels. Excluding I/O buffers, the chip occupies an area of 4.3 x 4.3 mm(2) and dissipates 909 mW from a 1.8 V supply.
A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background. calibration
(2006)
Lee, Zwei-Mei
;
Wang, Cheng-Yeh
;
Wu, Jieh-Tsorng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 15-bit 125-MS/s two-channel time-interleaved pipelined ADC is fabricated in a 0.18 mu m CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. The ADC uses a single sample-and-hold amplifier which employs a precharging circuit technique to mitigate the performance requirements for its opamp. Digital background calibration is applied to maintain the conversion linearity of each AID channel and also correct both gain and offset mismatches between the two channels. Excluding I/O buffers, the chip occupies an area of 4.3 x 4.3 mm(2) and dissipates 909 mW from a 1.8 V supply.
Pre-charge sample-and-hold circuit
(2008-07-31)
Wu, Jieh-Tsorng
;
Lee, Zwei-Mei
;
Wang, Cheng-Yeh
A precharge sample-and-hold circuit is formed by coupling a buffer with an input port and making use of a switch to conduct the circuit between the buffer and a total load capacitor for precharging according the state of a sample-and-hold circuit. When the sample-and-hold circuit is in the sample mode, it precharges the total load capacitor. When the sample-and-hold circuit is in the hold mode, the influence to the sampled signal is further reduced due to the precharging. The requirements of swing rate, output voltage swing, gain-bandwidth product for the opamps can therefore be reduced, hence being applicable to the realization of the design of advanced fabrication technologies of low supply voltages.