Browsing by Author "Lee Chen-Yi"

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Apparatus and method of processing polynomials
(2014-02-04)
Lin Yi-Min
;
Yang Chi-Heng
;
Chang Hsie-Chia
;
Lee Chen-Yi
An apparatus of processing polynomials includes at least one reconfigurable module and an encoder controller. The reconfigurable module includes a plurality of linear feedback shift registers. The encoder controller can control the reconfigurable module to factor a generator polynomial into a factorial polynomial. In the reconfigurable module, the linear feedback shift registers can register a plurality of factors of the factorial polynomial respectively.
CYCLIC CODE DECODING METHOD AND CYCLIC CODE DECODER
(2013-05-02)
Lin Yi-Min
;
Hsu Chih-Hsiang
;
Chang Hsie-Chia
;
Lee Chen-Yi
In a cyclic code decoding method, a decoder analyzes a received codeword to identify unreliable symbols in the codeword, and sets candidate syndrome patterns accordingly. Then, a syndrome calculator calculates evaluated syndrome values associated with one of the candidate syndrome patterns, and an error location polynomial (ELP) generator generates an ELP according to the syndrome values. An error correction device corrects the errors in the codeword according to theELP when a degree of the ELP is not more than a threshold value, and the syndrome calculator adjusts the syndrome values and the ELP generator generates another ELP according to the adjusted syndrome values when otherwise.
Cyclic code decoding method and cyclic code decoder
(2015-01-27)
Lin Yi-Min
;
Hsu Chih-Hsiang
;
Chang Hsie-Chia
;
Lee Chen-Yi
In a cyclic code decoding method, a decoder analyzes a received codeword to identify unreliable symbols in the codeword, and sets candidate syndrome patterns accordingly. Then, a syndrome calculator calculates evaluated syndrome values associated with one of the candidate syndrome patterns, and an error location polynomial (ELP) generator generates an ELP according to the syndrome values. An error correction device corrects the errors in the codeword according to the ELP when a degree of the ELP is not more than a threshold value, and the syndrome calculator adjusts the syndrome values and the ELP generator generates another ELP according to the adjusted syndrome values when otherwise.
DATA STORAGE DEVICE AND COMPUTING SYSTEM WITH THE SAME
(2015-04-23)
Wong Wing Hung
;
Wu Tung-Yu
;
Lee Chen-Yi
;
Chang Hsi-Chia
;
Hsu Shu-Yu
A data storage device is in communication with a host through a bus. The data storage device includes a storage medium and a controlling unit. The controlling unit is connected with the host and the storage medium for receiving an analysis data, or storing a write data into the storage medium or retrieving a read data from the storage medium to the host according to a command from the host. The controlling unit includes an arithmetic logic unit. The arithmetic logic unit has a built-in algorithm for analyzing and processing the analysis data, the write data or the read data, thereby generating an analysis result. Moreover, the algorithm may be updated or expanded by the host.
Delay cell and digitally controlled oscillator
(2013-06-18)
Lee Chen-Yi
;
Yu Chien-Ying
;
Yu Chia-Jung
A delay cell includes a first inverted transistor pair, a second inverted transistor pair and a plurality of delay units. The first inverted transistor pair is used to receive an input signal. The second inverted transistor pair is electrically cross-coupled to the first inverted transistor pair and cross-controlled by the first inverted transistor pair. The delay units are cascaded between the first inverted transistor pair and between the second inverted transistor pair, thereby providing a plurality of signal propagation delays sequentially, wherein the input signal is delayed for a pre-determined time by the first inverted transistor pair, the second inverted transistor pair and the delay units which are operated sequentially, thereby creating an output signal corresponding to the pre-determined time. A digitally controlled oscillator including the aforementioned delay cells is provided.
Digital sensing apparatus and digital readout module thereof
(2014-05-27)
Lai Kelvin Yi-Tse
;
Lee Chen-Yi
A digital sensing apparatus includes a sensing unit capable of providing a sensing response associated with an environmental parameter, and a digital readout module including a reading unit for generating a pulse signal having a pulse width associated with the sensing response, and a converting unit. The converting unit includes a clock signal generator for generating a variable-frequency clock signal, and a counter operable to count a width value of the pulse width of the pulse signal using the clock signal, so as to generate a digital sensing code. The frequency of the clock signal from the clock signal generator is adjustable to adjust resolution of the width value of the pulse width of the pulse signal.
Dual positive-feedbacks voltage controlled oscillator
(2011-11-10)
Lee Chen-Yi
A dual positive-feedbacks voltage controlled oscillator includes an oscillation circuit and a cross coupled pair circuit. The oscillation circuit includes a first transistor, a second transistor, an inductor and a plurality of capacitors. The gates of the first and second transistors are opposite to each other and coupled to two points of the inductor. The inductor and the capacitors are formed as a LC tank. The cross coupled pair circuit includes a third transistor and a fourth transistor. The gates of the third and fourth transistors are cross coupled to two points of the inductor. Thereby, the gate of the third transistor is coupled to the gate of the second transistor; the gate of the fourth transistor is coupled to the gate of the first transistor; the drain of the third transistor is coupled to the source of the first transistor; and the drain of the fourth transistor is coupled to the source of the second transistor.
Memory-based FFT/IFFT processor and design method for general sized memory-based FFT processor
(2013-01-29)
Lee Chen-Yi
;
Hsiao Chen-Fong
;
Chen Yuan
For a large size FFT computation, this invention decomposes it into several smaller sizes FFT by decomposition equation and then transform the original index from one dimension into multi-dimension vector. By controlling the index vector, this invention could distribute the input data into different memory banks such that both the in-place policy for computation and the multi-bank memory for high-radix structure could be supported simultaneously without memory conflict. Besides, in order to keep memory conflict-free when the in-place policy is also adopted for I/O data, this invention reverses the decompose order of FFT to satisfy the vector reverse behavior. This invention can minimize the area and reduce the necessary clock rate effectively for general sized memory-based FFT processor design.
Operating method and circuit for low density parity check (LDPC) decoder
(2012-01-31)
Liu Chih-Hao
;
Liao Yen-Chin
;
Lee Chen-Yi
;
Chang Hsie-Chia
;
Hsu Yarsun
An operating method and a circuit for low density parity check (LDPC) decoders, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the difference between the newly generated check messages and the previous check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. The required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.
Pulse-based flip flop
(2015-02-03)
Lee Chen-Yi
;
Sung Wei-Hao
;
Lee Ming-Che
A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a first clock signal and the second clock signal. The pulse-based flip-flop includes a pulse generator and a data latch. The pulse generator includes a first inverter and a signal delay circuit to receive the first clock signal and generate the second clock signal; the data latch includes a delivery circuit, a latch circuit and a control circuit. The data latch is used to latch the data input signal and output the data output signal in response to the first and the second clock signals.
SENSING SYSTEM AND SENSOR CHIP THEREOF
(2015-09-24)
Lee Chen-Yi
;
Lai Kelvin Yi-Tse
;
Yang Yu-Tao
A sensing system includes a processing unit and sensor chip. The sensor chip includes a microelectrode array, a droplet space over the microelectrode array, and a plurality of control units coupled together in a daisy-chain configuration. Each of the control units is coupled to a respective one of the microelectrodes of the microelectrode array. The control units are controlled by the processing unit to drive movement of a droplet in the droplet space, and to inspect the droplet via the microelectrodes.