Browsing by Author "Lei, TF"

Now showing 1 - 20 of 132

2-bit poly-Si-TFT nonvolatile memory using hafnium oxide, hafnium silicate and zirconium silicate
(2005)
Lin, YH
;
Chien, CH
;
Chou, TH
;
Chao, TS
;
Chang, CY
In this paper, we, for the first time, have successfully fabricated SONOS-type poly-Si-TFT memories employing three kinds of high-k dielectrics, including HfO(2), Hf-silicate and Zr-silicate, as the trapping layer with low-thermal budget processing. It was demonstrated that the fabricated memories exhibit good performance in terms of relatively large memory window, high program/erase speed (1ms/10ms), long retention time (> 10(6)S for 20% charge loss) and negligible read/write disturbances. In particular, 2-bit operation has been successfully demonstrated.
A novel dynamic threshold voltage MOSFET (DTMOS) using heterostructure channel of Si1-yCy interlayer
(2005-10-01)
Shieh, MS
;
Chen, PS
;
Tsai, MJ
;
Lei, TF
;
電子工程學系及電子研究所
We have demonstrated the fabrication of dynamic threshold voltage MOSFET (DTMOS) using the Si1-yCy(y = 0.005) incorporation inerlayer channel. Compare to conventional Si-DTMOS, the introduction of the Si1-yCy interlayer for this device is realized by super-steep-retrograde (SSR) channel profiles due to the retardation of boron diffusion. A low surface channel impurity with heavily doped substrate can be achieved simultaneously. This novel Si1-yCy channel heterostructure MOSFET exhibits higher transconductance and turn on current.
A novel planarization of oxide-filled shallow-trench isolation
(1997-01-01)
Cheng, JY
;
Lei, TF
;
Chao, TS
;
Yen, DLW
;
Lin, CJ
Two planarization approaches of the oxide-filled trench isolation have been evaluated. Results show that the oxide-filled shallow-trench isolation technology based on a chemical-mechanical polishing (CMP) process is difficult to control and has a poor uniformity. It also results in a dishing effect in wide field regions. On the other hand, a new planarization process can achieve an excellent uniformity and fully planar surface by using a combination of a masking polysilicon layer based on a CMP process, selective wet etching for oxide refill on active regions, short-time CMP process for oxide refill, and reactive ion etching etchback. Results also show that the high breakdown yield of the gate oxide and the low leakage current of the n(+)/p junction diodes with the novel planarization process demonstrates extremely low defect density from this process. This new process is a very promising candidate for oxide-filled shallow-trench isolation.
A novel process-compatible fluorination technique with electrical characteristic improvements of poly-Si TFTs
(2005-06-01)
Wang, SD
;
Lo, WH
;
Chang, TY
;
Lei, TF
;
電子工程學系及電子研究所
A process-compatible fluorine passivation technique of poly-Si thin-film transistors (TFTs) was demonstrated by employing a novel CF4 plasma treatment. Introducing fluorine atoms into poly-Si films can effectively passivate the trap states near the SiO2/poly-Si interface. With fluorine incorporation, the electrical characteristics of poly-Si TFTs can be significantly improved including a steeper subthreshold slope, smaller threshold voltage, lower leakage current, higher field-effect mobility, and better On/Off current ratio. Furthermore, the CF4 plasma treatment also improves the reliability of poly-Si TFTs with respect to hot-carrier stress, which is due to the formation of strong Si-F bonds.
A novel shallow trench isolation technique
(1997-03-01)
Cheng, JY
;
Lei, TF
;
Chao, TS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Shallow-trench isolation processes which involve refilling using deposition of oxide and polysilicon were investigated. Our results show that the oxide-filled shallow-trench isolation technology based on chemical-mechanical polishing (CMP) is difficult to control and results in poor uniformity. Use of this technology also involves in the dishing effect in wide field regions. However, shallow-trench isolation technology using a masking nitride layer, polysilicon refill, the CMP process with high etch selectivity, and local oxidation of polysilicon is easily implemented and absolutely field oxide encroachment (bird's beak) free. Although the CMP process results in the dishing effect in wide field regions, the local oxidation of polysilicon can reduce the amount of dishing. The polysilicon-filled shallow-trench isolation process can also achieve excellent uniformity across 6-inch diameter silicon wafers due to the high etching selectivity of polysilicon to chemical-vapor-deposited (CVD) oxide and SiN. Moreover, the n(+)/p junction leakage current of polysilicon-filled shallow trenches is comparable to that of oxide-filled shallow trenches. This simple and easily controllable process is a very promising candidate for shallow trench isolation.
A novel Si-B diffusion source for p(+)-poly-Si gate
(1999-10-01)
Chao, TS
;
Kuo, CP
;
Chen, TP
;
Lei, TF
;
電子工程學系及電子研究所
In this paper, we report a novel Si-B diffusion source for p(+)-polySi gate p-metal oxide-semiconductor field effect transistors (pMOSFETs). It is found that boron penetration can br effectively suppressed using this process. All the electrical properties of the MOS capacitors are significantly improved over the conventional BF2+ or B+-implanted samples. This process is very promising for fabrication of future surface-channel p-MOSFETs. (C) 1999 The Electrochemical Society. S0013-4651(99)03-017-7. All rights reserved.
A novel structure for three-dimensional silicon magnetic transducers to improve the sensitivity symmetry
(1996-09-01)
Lin, HY
;
Lei, TF
;
Jeng, JJ
;
Pan, CL
;
Chang, CY
A three-dimensional silicon magnetic transducer with symmetric sensitivities in the x-, y- and z-directions and small cross sensitivity has been demonstrated. Devices are based on a design of a vertical Hall structure using the surrounding trench and symmetric design to suppress the cross sensitivity. The fabrication process is simple and can be used as a part of a standard integrated circuit process. The results show that almost equal sensitivities in all three components of magnetic field can be obtained by coating Ni/Co thin films on the backside of the substrates. The cross sensitivity is only 1.3% of the sensitivity.
A novel structure for three-dimensional silicon magnetic transducers to improve the sensitivity symmetry
(1996-09-01)
Lin, HY
;
Lei, TF
;
Jeng, JJ
;
Pan, CL
;
Chang, CY
A three-dimensional silicon magnetic transducer with symmetric sensitivities in the x-, y- and z-directions and small cross sensitivity has been demonstrated. Devices are based on a design of a vertical Hall structure using the surrounding trench and symmetric design to suppress the cross sensitivity. The fabrication process is simple and can be used as a part of a standard integrated circuit process. The results show that almost equal sensitivities in all three components of magnetic field can be obtained by coating Ni/Co thin films on the backside of the substrates. The cross sensitivity is only 1.3% of the sensitivity.
A novel thin-film transistor with self-aligned field induced drain
(2001-01-01)
Lin, HC
;
Yu, CM
;
Lin, CY
;
Yeh, KL
;
Huang, TY
In this letter, a novel thin-film transistor with a self-aligned field-induced-drain (SAFID) structure is reported for the first time. The new SAFID TFT features a self-aligned sidewall spacer located on top of the drain offset region to set its effective length, and a bottom gate (or field plate) situated under the drain offset region to electrically induce the field-induced-drain (FID). So, unlike the conventional off-set-gated TFTs with their effective FID length set by two separate photolithographic masking layers, the new SAFID is totally immune to photomasking misalignment errors, while enjoying the low off-state leakage as well as high turn-on characteristics inherent in the FID structure. Polycrystalline silicon TFTs with the new SAFID structure have been successfully fabricated with significant improvement in the on/off current ratio.
A novel vertical bottom-gate polysilicon thin film transistor with self-aligned offset
(1996-05-01)
Lai, CS
;
Lee, CL
;
Lei, TF
;
Chern, HN
;
電子工程學系及電子研究所
A novel device structure for the vertical bottom polysilicon gate thin film transistor (TFT) with a self-align offset drain is proposed and demonstrated, The new VTFT allows a deep-submicron channel length, which is determined by the thickness of the active polysilicon film, not by the lithographic system resolution, The self-alignment offset drain reduces the leakage current, as a result, it exhibits good device performance.
A one-step single-cleaning solution for CMOS processes
(2003-09-01)
Chao, TS
;
Yeh, CH
;
Pan, TM
;
Lei, TF
;
Li, YH
In this paper, we demonstrate a one-step single-cleaning solution to replace the conventional RCA two-step cleaning method for complementary metal oxide semiconductor (CMOS) processes. We found the performance of devices fabricated using this new recipe is comparable or even better than that of devices fabricated using the conventional RCA method. The benefits of this method are more efficient removal of contaminants, improved driving current of devices, simpler processing, fewer steps in cleaning, time savings, reduction of cost and of chemical waste, and reduced impact on the environment. (C) 2003 The Electrochemical Society.
A physical model for the hysteresis phenomenon of the ultrathin ZrO2 film
(2002-10-01)
Wang, JC
;
Chiao, SH
;
Lee, CL
;
Lei, TF
;
Lin, YM
This work studies and presents an inner-interface trapping physical model for the ultra-thin (effective oxide thickness=15 Angstrom) zirconium oxide (ZrO2) film to explain its hysteresis phenomenon. The shift of the capacitance-voltage characteristics swept from accumulation to inversion and then swept back with light illumination is about 110 mV, which is larger than the shift without light illumination (similar to45 mV). The mobile ion effect is obviated using bias-temperature stress measurement. The proposed model successfully explains not only the phenomenon but also the thickness effect for the capacitance-voltage characteristics and the different turn-around voltages of the current density-voltage characteristics of the zirconium dielectrics. (C) 2002 American Institute of Physics.
An investigation of scanning capacitance microscopy on iron-contaminated p-type silicon
(2001-09-01)
Chang, MN
;
Chang, TY
;
Pan, FM
;
Wu, BW
;
Lei, TF
Scanning capacitance microscopy (SCM) is employed to examine iron-contaminated p-type Si samples. For slightly contaminated samples, a dc voltage of -0.8 V, applied between the sample and the conductive tip, induces positive trapped charges. Owing to the existence of these charges, the region containing trapped charges exhibits an obviously low dC/dV signal. According to contact-mode atomic force microscopy results, the surface, morphology has little effect on the SCM signal. The experimental results indicate that SCM is capable of detecting the distribution of oxidation-related. defects which cannot otherwise be easily observed by atomic force microscopy and transmission electron microscopy. (C) 2001 The Electrochemical Society.
Annealing temperature effect on the performance of nonvolatile HfO2Si-oxide-nitride-oxide-silicon-type flash memory
(2006-05-01)
Lin, YH
;
Chien, CH
;
Chang, CY
;
Lei, TF
;
電子工程學系及電子研究所
In this article, we demonstrate the effect of the postdeposition annealing for the HfO2 trapping layer on the performance of the Si-oxide-nitride-oxide-silicon-type flash memories. It was found that the memory window becomes larger while the retention and endurance characteristics get worse as the annealing temperature increases. This was ascribed to the larger amount and the shallower energy levels of the crystallization-induced traps as compared to the traps presented in the as-fabricated HfO2 film. Finally, in the aspect of disturbances, we show only insignificant read, drain, and gate disturbances presented in the three samples in the normal operation. (c) 2006 American Vacuum Society.
Carrier transportation of rapid thermal annealed CeO2 gate dielectrics
(2004)
Wang, JC
;
Chiang, KC
;
Lei, TF
;
Lee, CL
;
電子工程學系及電子研究所
We investigated the carrier transportation of ultrathin CeO2 gate dielectrics with rapid thermal annealing (RTA). After annealing, the effective oxide thickness was decreased and the characteristics were significantly improved. Temperature dependence of gate leakage current was studied and Frenkel-Poole dominated the conduction mechanism for low RTA temperature. As the annealing temperature increases, Fowler-Nordheim tunneling became much more important and the CeO2/n-Si electron barrier height of 0.75 eV was extracted for future modeling and simulation. In addition, the energy band diagram of Al/CeO2/n-Si structure was established for the first time. (C) 2004 The Electrochemical Society.
CF4 plasma treatment for fabricating high-performance and reliable solid-phase-crystallized poly-Si TFTs
(2005)
Wang, SD
;
Lo, WH
;
Lei, TF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A CF4 plasma treatment on solid-phase-crystallized (SPC) poly-Si thin-film transistors ( TFTs ) has been demonstrated. Using this technique, fluorine atoms can be introduced into the poly-Si film to passivate the defects, and hence, the device performance of the SPC poly-Si TFTs can be significantly improved. The fluorinated SPC poly- Si TFTs exhibit a good subthreshold slope, low threshold voltage, and high field effect mobility. Moreover, the fluorinated SPC poly- Si TFTs also exhibit an improved hot-carrier-stress immunity, which is due to the strong Si-F bonds formed in the poly-Si channel region. (c) 2005 The Electrochemical Society.
Characteristics improvement and carrier transportation of CeO2 gate dielectrics with rapid thermal annealing
(2004)
Wang, JC
;
Chiang, KC
;
Lei, TF
;
Lee, CL
;
電子工程學系及電子研究所
In this paper, we have investigated the properties and carrier transportation of ultra-thin cerium dioxide films with rapid thermal annealing. Improved characteristics such as low leakage current, high breakdown voltage and large time-dependent-dielectric-breakdown (TDDB) are obtained owing to the more stoichiometric of the CeO2 films after high temperature annealing. Moreover, temperature dependence of gate leakage current under substrate injection is studied, and the carrier conduction mechanisms, including the Frenkel-Poole (F-P) conduction and the Fowler-Nordheim (F-N) tunneling are also proposed, from which we have deduced the energy band diagram of Al/CeO2/n-Si structure for the first time.
Characteristics of polycrystalline silicon thin-film transistors with electrical source/drain extensions induced by a bottom sub-gate
(2002-05-01)
Yu, M
;
Lin, HC
;
Chen, GH
;
Huang, TY
;
Lei, TF
Characteristics of polycrystalline silicon thin-film transistors (TFT) with source/drain extensions induced by a bottom sub-gate were explored, high on/off current ratio up to 10(7) could be achieved for both n- and p-channel devices. Nevertheless, the performance is significantly degraded by a marked increase of off-state leak-age current when the channel length is scaled below 1 mum. Moreover, a hump in the subthreshold current-voltage regime is observed. After careful analysis, it is found that the leakage current is strongly dependent on the field strength and is not a thermally activated process. A leakage path along the bottom interface of the poly-Si channel layer is proposed to explain these results.
Characteristics of polysilicon oxides combining N2O nitridation and CMP processes
(2000-08-01)
Lei, TF
;
Chen, JH
;
Wang, MF
;
Chao, TS
;
電子工程學系及電子研究所
This paper present a high-quality polysilicon oxide combining N2O nitridation and chemical mechanical polishing (CMP) processes. Experimental results indicate that polyoxide grown on the CMP sample exhibits a lower leakage current, higher dielectric breakdown field, higher electron barrier height, less electron trapping rate, higher charge-to-breakdown (Q(bd)), and lower density of trapping charge than those of non-CMP samples. In addition, the CMP process enhances nitrogen incorporation at the interface by the N2O nitridation, ultimately improving the polyoxide quality, Moreover, the CMP process smooths the surface of polysilicon and this planar surface reduces the out-diffusion of the phosphorous during thermal oxidation.
Characteristics of TEOS polysilicon oxides: Improvement by CMP and high temperature RTA N-2/N2O annealing
(2000-11-01)
Chen, JH
;
Lei, TF
;
Chen, JH
;
Chao, TS
;
電子工程學系及電子研究所
The integrity of tetraethylorthosilicate (TEOS) polyoxide using chemical mechanical polishing (CMP) plus a high temperature rapid thermal annealing (RTA) step was studied in this work. The surface morphology of polysilicon is improved after a CMP process. Polyoxides deposited by low pressure chemical vapor deposition (LPCVD) TEOS in conjunction with CMP and RTA N-2/N2O annealing exhibit a better current-electric field (J-E) curve, higher charge to breakdown ratio, and lower electron trapping rate. In addition, the composite bilayer (TEOS deposited and thermally grown by RTA) polyoxide film introduces an asymmetry of electrical leakage current, trapping characterization, and charge to breakdown, with respect to the injection of different polarity (+V-g and -V-g) (C) 2000 The Electrochemical Society. S0013-4651(00)01-051-X. All rights reserved.