Browsing by Author "Li, Bing"

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ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing
(2015-06-01)
Tseng, Tsun-Ming
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Li, Bing
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Ho, Tsung-Yi
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Schlichtmann, Ulf
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交大名義發表
Length-matching is an important technique to balance delays of bus signals in high-performance printed circuit board (PCB) routing. Existing routers, however, may generate very dense meander segments. Signals propagating along these meander segments exhibit a speedup effect due to crosstalk between the segments of the same wire, thus leading to mismatch of arrival times even under the same physical wire length. In this paper, we present a post-processing method to enlarge the width and the distance of meander segments and hence distribute them more evenly on the board so that crosstalk can be reduced. In the proposed framework, we model the sharing of available routing areas after removing dense meander segments from the initial routing, as well as the generation of relaxed meander segments and their groups for wire length compensation. This model is transformed into an ILP problem and solved for a balanced distribution of wire patterns. In addition, we adjust the locations of long wire segments according to wire priorities to swap free spaces toward critical wires that need much length compensation. To reduce the problem space of the ILP model, we also introduce a progressive fixing technique so that wire patterns are grown gradually from the edge of the routing toward the center area. Experimental results show that the proposed method can expand meander segments significantly even under very tight area constraints, so that the speedup effect can be alleviated effectively in high-performance PCB designs.
Reliability, Adaptability and Flexibility in Timing: Buy a Life Insurance for Your Circuits
(2016)
Schlichtmann, Ulf
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Hashimoto, Masanori
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Jiang, Iris Hui-Ru
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Li, Bing
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交大名義發表
At nanometer manufacturing technology nodes, process variations affect circuit performance significantly. In addition, performance deterioration of circuits due to aging effects is also increasing. Consequently, a large timing margin is required to maintain yield. To combat the pessimism and the resulting overdesign, aging analysis with high-level models, on-chip timing margin monitoring and tuning, and flexible delay models of flip-flops can be deployed. This paper gives an overview of the state of the art of applying these techniques to improve the health of circuits.
Reliability-aware Synthesis for Flow-based Microfluidic Biochips by Dynamic-device Mapping
(2015)
Tseng, Tsun-Ming
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Li, Bing
;
Ho, Tsung-Yi
;
Schlichtmann, Ulf
;
資訊工程學系
On flow-based biochips, valves that are used to form peristaltic pumps wear out much earlier than valves for transportation since the former are actuated more often, which leads to a reduced lifetime of the chip. In this paper, we introduce a valve-role-changing concept to avoid always using the same valves for peristalsis. Based on this, we generate dynamic devices from a valve-centered architecture to distribute the valve actuation activities evenly and reduce the largest number of valve actuations with even fewer valves. In addition, we propose in situ on-chip storages, which can overlap with other devices, so that less area is needed compared with dedicated storages on traditional chips. Moreover, our method provides good support for assays requiring different volumes and ratios of samples. Experiments show that compared with traditional designs, the largest number of valve actuations can be reduced by 72.97% averagely, while the number of valves is reduced by 10.62%.