Browsing by Author "Li, C. I."

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A New and Simple Experimental Approach to Characterizing the Carrier Transport and Reliability of Strained CMOS Devices in the Quasi-Ballistic Regime
(2009)
Hsieh, E. R.
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Chung, Steve S.
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Liu, P. W.
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Chiang, W. T.
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Tsai, C. H.
A new yet simple approach, V(D,sat) method, without complicate temperature measurement setup, has been developed to investigate the carrier transport characteristics for MOSFET devices in the quasi-ballistic regime. It has shown quite good matches with that of Temperature Dependent Method (TDM) developed from the quantum theory [1]. For the first time, the carrier transport properties after HC stress were also examined based on the proposed method. Moreover, method has been applied to examine the carrier transport and reliabilities in advanced strain-CMOS devices. In terms of the device performance, the enhancement of the drain current is strongly related to the transport parameter, the injection velocity, V(inj) which serves as a good monitor for the strain design and current enhancement. While, considering the device reliability after the HC stress, ballistic efficiency, B(sat) is responsible for the I(D) degradation as a result of the increase in interface scatterings. Finally, a roadmap of the V(inj) from those reported results has been provided which serves as a good reference for designing high performance strain-based CMOS devices.
Design of High-Performance and Highly Reliable nMOSFETs with Embedded Si:C S/D Extension Stressor(Si:C S/D-E)
(2009)
Chung, Steve S.
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Hsieh, E. R.
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Liu, P. W.
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Chiang, W. T.
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Tsai, S. H.
A Novel strained nMOSFET with embedded Si:C in S/D extension stressor (Si:C S/D-E) was presented. Comparing to the bulk device, it revealed good drive current ION (+27%), high I(D.sat) current (+67%), enhanced channel mobility (+105%), at a lower effective substitutional carbon concentration (C%-1.1%), using the poly-gate 40nm-node Si:C/eSiGe S/D CMOS technology. Moreover. PBTI effect was first observed in this device as a result of Carbn impurity out-diffusion, which is of critically important for the design trade-off between performance and reliability.
Suppressing Device Variability by Cryogenic Implant for 28-nm Low-Power SoC Applications
(2012-10-01)
Yang, C. L.
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Tsai, C. H.
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Li, C. I.
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Tzeng, C. Y.
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Lin, G. P.
In this letter, we have demonstrated that cryogenic implant in the source and drain formation offers advantages for reducing the threshold voltage mismatch in pMOSFET. A discrete dopant profiling method is used to verify the presence of boron out-diffusion from the drain, which further induces the random dopant fluctuation. Results show that this boron out-diffusion can be greatly reduced in this new process. Two major factors in improving the device variability by cryogenic implant are discussed, i.e., the polysilicon grain size control and the embedded-SiGe dislocation defect reduction during source and drain formation.