Browsing by Author "Li, Chun-Hsing"

Now showing 1 - 20 of 26

16.9-mW 33.7-dB Gain mm Wave Receiver Front-End in 65 nm CMOS
(2012)
Li, Chun-Hsing
;
Kuo, Chien-Nan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work presents a low power receiver front-end design for the 77 GHz radar application. The theoretical maximum achievable gains in the LNA and the mixer are derived by using energy conservation principle. It is shown that the maximum gain can be increased by raising the impedance ratio between stages. The impedance transformation is able to provide high passive gain without any power consumption. Moreover, the quality of the passive components plays a critical role to approach the maximum gain condition. Accordingly a low power receiver front-end is designed in 65 nm CMOS. The measured results show the highest gain of 33.7 dB at 73 GHz with 3 dB bandwidth from 67 GHz to 75 GHz. The input return loss, P1dB, IIP3, and NF at IF frequency of 8 MHz, are 16.4 dB, -32 dBm, -19 dBm, and 12.2 dB, respectively. The power consumption is only 16.9 mW from a 1 V supply. To the best of our knowledge, this work shows the highest gain while consumes the lowest power as compared to the prior works.
A 0.6-V 0.33-mW 5.5-GHz Receiver Front-End Using Resonator Coupling Technique
(2011-06-01)
Li, Chun-Hsing
;
Liu, Yen-Lin
;
Kuo, Chien-Nan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this study, a low-power and low-voltage 5.5-GHz receiver front-end circuit is designed using a resonator coupling technique. An on-chip transformer combined with the parasitic capacitances from a low-noise amplifier (LNA), a mixer, and the transformer itself comprises two coupled resonators of the resonator coupling network (RCN). The RCN functions as a balun, and couples energy from the LNA to the mixer. Under the critical coupling condition, the RCN gives a maximal current gain at resonance frequencies, equivalent to the same level by an ideal transformer. The analysis shows that the current gain is quite tolerable to the coupling coefficient variation, an advantageous feature for on-chip transformer design. The technique is verified by the receiver front-end in 0.18-mu m CMOS technology. The RCN possess a current gain as high as 12 dB at 5.5 GHz. The measured input return loss, conversion gain, and third-order intermodulation intercept point of the entire circuit are 16 dB, 17.4 dB, and -1.5 dBm, respectively. The noise figure is 7.8 dB at the IF frequency of 1 MHz. The power consumption is only 0.33 mW from a 0.6-V supply. The required local oscillator power is only -9.5 dBm. This receiver front-end successfully demonstrates the resonator coupling technique.
A 1.2-V 5.2-mW 20-30-GHz Wideband Receiver Front-End in 0.18-mu m CMOS
(2012-11-01)
Li, Chun-Hsing
;
Kuo, Chien-Nan
;
Kuo, Ming-Ching
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a low-power wideband receiver front-end design using a resonator coupling technique. Inductively coupled resonators, composed of an on-chip transformer and parasitic capacitances from a low-noise amplifier, a mixer, and the transformer itself, not only provide wideband signal transfer, but also realize wideband high-to-low impedance transformation. The coupled resonators also function as a wideband balun to give single-to-differential conversion. Analytic expressions for the coupled resonators with asymmetric loads are presented for design guidelines. The proposed receiver front-end only needs a few passive components so that gain degradation caused by the passive loss is minimized. Hence, power consumption and chip area can be greatly reduced. The chip is implemented in 0.18-mu m CMOS technology. The experimental result shows that the -3-dB bandwidth can span from 20 to 30 GHz with a peak conversion gain of 18.7 dB. The measured input return loss and third-order intercept point are better than 16.7 dB and -7.6 dBm, respectively, over the bandwidth. The minimum noise figure is 7.1 dB. The power consumption is only 5.2 mW from a 1.2-V supply. The chip area is only 0.18 mm(2).
A 147 GHz Fully Differential D-Band Amplifier Design in 65 nm CMOS
(2013)
Li, Chun-Hsing
;
Lai, Chih-Wei
;
Kuo, Chien-Nan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work presents a 147 GHz D-band fully differential amplifier design in 65 nm CMOS. By using a T-network, composed of three inductors, to replace an on-chip transformer, the proposed impedance transformation network can provide an impedance transformation ratio larger than one. So the passive gain can be acquired to increase the amplifier gain. The measured results show that the amplifier can provide power gain of 7.1 dB at 147 GHz. The power consumption is 104 mW from a 2 V supply voltage.
A 210-GHz Amplifier in 40-nm Digital CMOS Technology
(2013-06-01)
Ko, Chun-Lin
;
Li, Chun-Hsing
;
Kuo, Chien-Nan
;
Kuo, Ming-Ching
;
Chang, Da-Chiang
This paper presents a 210-GHz amplifier design in 40-nm digital bulk CMOS technology. The theoretical maximum voltage gain that an amplifier can achieve and the loss of a matching network are derived for the optimization of a few hundred gigahertz amplifiers. Accordingly, the bias and size of transistors, circuit topology, and inter-stage coupling method can be determined methodically to maximize the amplifier gain. The measured results show that the amplifier exhibits a peak power gain of 10.5 dB at 213.5 GHz and an estimated 3-dB bandwidth of 13 GHz. The power consumption is only 42.3 mW under a 0.8-V supply. To the best of the authors' knowledge, this work demonstrates the CMOS amplifier with highest operation frequency reported thus far.
A 340 GHz Triple-Push Oscillator With Differential Output in 40 nm CMOS
(2014-12-01)
Li, Chun-Hsing
;
Ko, Chun-Lin
;
Kuo, Chien-Nan
;
Kuo, Ming-Ching
;
Chang, Da-Chiang
A low-power triple-push oscillator with differential output is proposed in this letter. By extracting signals from the same current loop, the oscillator can naturally provide differential output without any additional active circuit or passive balun required. Therefore, the output power can be increased and the chip area and power consumption can be reduced. Realized in 40 nm CMOS technology, the proposed oscillator can oscillate at 340.6 GHz while providing equivalent isotropically radiated power (EIRP) as -21.8 dBm. The power consumption is only 34.1 mW from a 0.9 V supply. The oscillator core only occupies area of 0.028 mm(2).
A 37.5-mW 8-dBm-EIRP 15.5 degrees-HPBW 338-GHz Terahertz Transmitter Using SoP Heterogeneous System Integration
(2015-02-01)
Li, Chun-Hsing
;
Chao, Tzu-Yuan
;
Lai, Chih-Wei
;
Chen, Wei-Cheng
;
Ko, Chun-Lin
A low-cost terahertz transmitter is proposed by using system-on-package (SoP) heterogeneous system integration. A signal source in 40-nm CMOS is integrated with an antenna array on a Benzocyclobutene carrier through a broadband low-loss terahertz interconnect. The signal source adopting triple-push oscillator topology is able to produce a differential output without any additional balun circuit. Hence, the power consumption and the chip area can be reduced. The antenna array containing 50 patch antennas is differentially excited to give simulated directivity, efficiency, and antenna gain as high as 22.6 dB, 88%, and 22 dBi, respectively, at 335 GHz. The terahertz interconnect employs a resonator coupling technique to provide low-loss and broadband performance while occupying a small area. Measured results show that the proposed terahertz transmitter can work at 338.4 GHz with equivalent isotropically radiated power (EIRP) of 8.0 dBm while consuming only 37.5 mW from a 1-V supply. The measured half-power beam-width can be as narrow as 15.5 degrees. The EIRP can be further raised to 9.5 dBm as the supply V-DD is increased to 1.3 V. The CMOS chip only occupies an area as small as 0.028 mm(2). All of the design efforts enable the proposed terahertz transmitter to feature in small form factor, low power dissipation, low cost, and high performance. To the best of the authors\' knowledge, this is the most compact, lowest power, lowest cost, and high-performance SoP-based terahertz transmitter reported thus far.
A 8-mW 77-GHz Band CMOS LNA by Using Reduced Simultaneous Noise and Impedance Matching Technique
(2015)
Ko, Chun-Lin
;
Li, Chun-Hsing
;
Kuo, Chien-Nan
;
Kuo, Ming-Ching
;
Chang, Da-Chiang
This paper presents analysis and design of source inductance for multistage LNA at 77-GHz band in 90 nm CMOS technology. Instead of simultaneous noise and impedance matching, the analysis shows the optimum degeneration of the single stage design for millimeter-wave frequencies. A low-power 77-GHz band LNA has been demonstrated to verify the optimization result. By using the proposed method, the LNA exhibited a low noise figure of 5.1 dB and a gain of 18.1 dB at 78.5 GHz with only 8 mW from a 1-V power supply.
A Broadband Interconnect for THz Heterogeneous System Integration
(2013)
Li, Chun-Hsing
;
Wu, Jan-Jr
;
Kuo, Chien-Nan
;
Cheng, Yu-Ting
;
Kuo, Ming-Ching
A broadband interconnect for THz heterogeneous system integration is proposed using a resonator coupling technique. Two resonators, deployed on a chip and a carrier, respectively, are coupled through the electromagnetic field to provide a low-loss interconnect in a broadband manner. Simulation results indicate an insertion loss of 0.32 dB at 170 GHz while covering 3-dB bandwidth from 100 to 344 GHz. Measurement can be conducted to verify its performance only from 140 GHz to 220 GHz, due to equipment limit. The measured minimum insertion loss is 0.47 dB at 164 GHz.
A Flip-Chip-Assembled W-Band Receiver in 90-nm CMOS and IPD Technologies
(2019-04-01)
Li, Chun-Hsing
;
Hsieh, Wan-Ting
;
Chiu, Te-Yen
;
交大名義發表
;
National Chiao Tung University
A flip-chip-assembled W-band receiver composed of a 90-nm CMOS chip and an integrated-passive-device (IPD) carrier is presented in this paper. The chip which integrates a low-noise amplifier, a single-sideband mixer, a frequency doubler (FD), and a wide-band variable-gain amplifier, is flip-chip packaged to the IPD carrier through a low-loss interconnect. The simulated loss of the interconnect without any compensation network is only 0.95 dB at 94 GHz. The FD can provide differential output without any additional lossy balun required, effectively increasing the FD output power, and hence relaxing the local oscillator generation circuit design. The experimental results show that the proposed packaged receiver can provide a variable gain from 11.3 to 48.2 dB, while having an input 1-dB compression point from -43.7 to -29 dBm as the RF frequency is 90 GHz. The intermediate bandwidth and minimum noise figure can be 1.0 GHz and 7.8 dB, respectively. The proposed receiver only consumes 73.9 mW from a 1.2-V supply. As compared with prior works, the proposed receiver exhibits higher gain, lower noise, and lower power dissipation even though a less-advanced 90-nm CMOS technology is adopted. To the best of the authors' knowledge, this is the first W-band CMOS receiver assembled on an IPD carrier reported thus far.
A High Q On-Chip Bondwire Transformer and Its Application to Low Power Receiver Front-End Design
(2013)
Li, Chun-Hsing
;
Kuo, Chien-Nan
;
Kuo, Ming-Ching
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work presents a high Q on-chip bondwire transformer and its application to a low power receiver front-end design. The proposed bondwire transformer has the advantage of high quality factor, less sensitivity to the bonding height variation, and working as a balun to conduct single-to-differential conversion. Furthermore, the chip area under the bondwire transformer can be reused by the mixer and buffer circuits to reduce the cost. The receiver front-end is realized in 1P6M 0.18 mu m CMOS technology. The measured input return loss, the conversion gain, the noise figure, and the input third-order intercept point are 12.7 dB, 20.5 dB, 9.8 dB, and -4.0 dBm, respectively, at 2.1 GHz. The power consumption is only 1.1 mW from a 1 V supply.
A Low-Cost Broadband Bondwire Interconnect for Heterogeneous System Integration
(2013)
Li, Chun-Hsing
;
Ko, Chun-Lin
;
Kuo, Chien-Nan
;
Kuo, Ming-Ching
;
Chang, Da-Chiang
A low-cost broadband interconnect, composed of bondwires and transmission lines, is proposed for heterogeneous system integration. By designing the length and the characteristic impedance of the transmission lines, the bondwire effect can be reduced to provide an interconnect with good return loss and low insertion loss. In this work, the chip and the carrier are realized in 90-nm CMOS and GIPD process, respectively. Measured results show that the return loss and the insertion loss are better than 10 dB and 1.1 dB, respectively, from DC to 45.2 GHz.
A Low-Cost Broadband Bondwire Interconnect for THz Heterogeneous System Integration
(2015)
Li, Chun-Hsing
;
Lai, Chih-Wei
;
Yan, Tzu-Chao
;
Kuo, Chien-Nan
;
電機工程學系
A low-cost broadband bondwire interconnect is proposed for THz heterogeneous system integration. A transversal path composed of two transmission lines and a bondwire is introduced to effectively reduce the bondwire effect of an original signal path consisted of a single bondwire only. Simulation results indicate that the return loss and insertion loss can be better than 15 dB and 2.3 dB from dc to 456 GHz, respectively. Measured interconnect loss is around 0 dB to 1.5 dB from 320 to 340 GHz.
A Low-Cost DC-to-84-GHz Broadband Bondwire Interconnect for SoP Heterogeneous System Integration
(2013-12-01)
Li, Chun-Hsing
;
Ko, Chun-Lin
;
Kuo, Chien-Nan
;
Kuo, Ming-Ching
;
Chang, Da-Chiang
A low-cost broadband bondwire interconnect is proposed for heterogeneous system integration. Transmission lines are incorporated with bondwires to form a two-path structure, which can effectively reduce the bondwire effect. Theoretical analysis is provided using a graphical method and it shows that the interconnect can give widest operation bandwidth from dc up to a maximum frequency f(max) if the length of the transmission lines is designed at an optimal electrical length theta(max) . In particular, theta(max) only depends on the characteristic impedance of the transmission lines. The achievable f(max) is limited by the bondwire inductance, i.e., smaller bondwire inductance is preferred to have wider operation bandwidth. An interconnect from a 0.18-mu m CMOS chip to a glass-integrated-passive-device carrier is designed to verify the proposed concept. Measured results show that the insertion loss and the return loss can be better than 3.0 and 13.4 dB, respectively, from dc to 84 GHz. The proposed interconnect shows around 3.2 times bandwidth of a single bondwire alone. To the best of authors' knowledge, this work demonstrates the bondwire interconnect with the widest operation bandwidth for heterogeneous system integration by using system-on-package reported thus far.
An Interconnecting Technology for RF MEMS Heterogeneous Chip Integration
(2010-04-01)
Chao, Tzu-Yuan
;
Li, Chun-Hsing
;
Chen, Yang Chuan
;
Chen, Hsin-Yu
;
Cheng, Yu-Ting
An interconnecting technology using a Au-Au thermocompressive bond has been successfully developed for microelectromechanical system (MEMS) heterogeneous chip integration in this paper. The Daisy chain and RF transition structures are both designed and fabricated for the electrical characterization of the interconnect scheme. Measured dc contact resistance is about 14 +/- 5 m Omega for the bonding interface of Ni (1 mu m)/Au (0.4 mu m)/Au (0.4 mu m)/Ni (1 mu m) with a pad size of 40 mu m in diameter. The electrical transition between two chips, which have coplanar waveguides (CPWs) and microstrip lines, respectively, can be well interconnected with less than -15 dB return loss and -1.8 dB insertion loss up to 50 GHz without implementing complex structure designs and extra impedance matching networks in the transition by employing this technology. Meanwhile, it is found that the mechanical strength for the interconnecting bond can be as large as 100 MPa. A low-power RF low-noise amplifier has been successfully designed, fabricated, and utilized in this paper to demonstrate the feasibility of the interconnecting technology for RF MEMS heterogeneous chip integration by integrating a Taiwan Semiconductor Manufacturing Corporation 0.18-mu m RF complimentary metal-oxide-semiconductor chip with a silicon carrier, where high Q MEMS inductors are fabricated and utilized for good circuit performance in terms of excellent impedance matching, power gain, and gain flatness.
Broadband flip-chip interconnects for millimeter-wave Si-carrier System-on-Package
(2007)
Li, Chun-Hsing
;
Fu, Chang Tsung
;
Chao, Tzu-Yuan
;
Kuo, Chien-Nan
;
Cheng, Y. T.
A flip-chip interconnect is proposed to achieve good electrical performance applicable to millimeter-wave applications. By Au-Au thermocompression technique, the transition structure provides continuity of characteristic impedance from the on-carrier CPW line to the on-chip microstrip tine, as well as smooth current flow. Parameter optimization further indicates that the tapered reference ground connection is insensitive to the frequency response. Characterization of the structure is conducted by the THUR-REFLECT-LINE (TRL) calibration technique to test the flip-chip interconnects up to 50GHz. Measurement results show that return loss is better than 15dB and insertion loss smaller than 1.7dB up to 50GHz. The broadband transition structure is suitable for high frequency application without any external matching network.
CMOS THz Transmissive Imaging System
(2014)
Yan, Tzu-Chao
;
Li, Chun-Hsing
;
Lai, Chih-Wei
;
Chen, Wei-Cheng
;
Chao, Tzu-Yuan
This paper presents a THz imaging system composed of a signal source and a signal sensor in CMOS technology The signal source integrates a 338 GHz oscillator in 40-nm CMOS and an antenna array on a Benzocyclobutene (BCB) carrier using the SoP (System-on-Package) technique. The measured EIRP achieves +8 dBm. The signal sensor is implemented in 0.18 mu m CMOS. The measured maximum responsivity is 632 kV/W at 332 GHz. The signal source and signal sensor consume dc power of 37.5 mW and 7.92 mW, respectively. The resolution of the proposed THz imaging system is 4 mm.
Design Optimization of a 1.4 GHz Low Power Bulk-Driven Mixer
(2010-01-01)
Li, Chun-Hsing
;
Kuo, Chien-Nan
;
電機學院
;
電子工程學系及電子研究所
;
College of Electrical and Computer Engineering
This work presents a design and analysis of a bulk-driven mixer using variant Volterra series approach. Topologies of the bulk-driven mixer (BDM) with and without a current source have been investigated. The analysis shows that the LO voltage swing has a limit in the BDM with a current source due to turn-on of the bulk-to-source diode. The operational principle of the BDM without a current source is discussed and indicates that it shall be characterized in terms of weakly nonlinear operation. With the insight gained from the nonlinear analysis, the proposed BDM is designed and implemented in 0.18-um CMOS technology. The measurement result shows that the voltage conversion gain, SSB noise figure, and IIP3 are 16 dB, 19.65 dB, and -0.5 dBm, respectively. The power consumption is only 0.25 mW from a supply voltage of 1 V.
Electronic THz Transmissive Imaging System
(2015)
Chen, Wei-Cheng
;
Lai, Chih-Wei
;
Yan, Tzu-Chao
;
Li, Chun-Hsing
;
Chao, Tzu-Yuan
An electronic THz transmissive imaging system is presented in this work. This system is composed of a CMOS signal source, a CMOS signal sensor, lenses, and commercial electronic chopping components. The output frequency of the signal source is 339 GHz, and the responsivity of the signal sensor is 200 kV/W. The total dc power consumption of those CMOS circuits is 91.02 mW. Using electronic chopping at the frequency up to 100 kHz helps improve the system dynamic range and makes imaging feasible. The resolution of the realized imaging system achieves 2 mm.
Enhancement of CMOS THz Imaging Sensing By Packaging Technology
(2017-01-01)
Kuo, Chien-Nan
;
Chen, Wei-Cheng
;
Chiu, Te-Yen
;
Li, Chun-Hsing
;
電子工程學系及電子研究所
Terahertz imaging sensing provides numerous attractive applications in different areas, for example, biology and medicine. CMOS technology benefits an imaging system in low cost and a small form factor. The technology advance is technically viable for circuit design in such high frequencies. Lossy silicon substrate, however, still degrades system performance. We will discuss the techniques of performance enhancement.