Browsing by Author "Li, Fu-Hai"

Now showing 1 - 8 of 8

3D Device Simulation of Work Function and Interface Trap Fluctuations on High-kappa/Metal Gate Devices
(2010)
Cheng, Hui-Wen
;
Li, Fu-Hai
;
Han, Ming-Hung
;
Yiu, Chun-Yen
;
Yu, Chia-Hui
This work, for the first time, examines the work function fluctuation (WKF) and interface trap fluctuation (ITF) using experimentally calibrated 3D device simulation on high-kappa / metal gate technology. The random WKs result in 36.7 mV threshold voltage fluctuation (sigma V(th)) for 16 nm N-MOSFETs with TiN gate, which is rather different from the result of averaged WKF (AWKF) method [1] due to localized random WK effect. The ITF affects the subthreshold region (the normalized sigma I(D) > 48%) and is suppressed for devices under strong inversion. Estimation of statistical covariance confirms the dependence of IT on the metal gate's WK; thus, the impacts of WKF and ITF on device and circuit variability should be considered together properly. Such variability induced static noise margin fluctuation of SRAM exceeds the influence of random dopants and cannot be ignored.
A New Programming Scheme for the Improvement of Program Disturb Characteristics in Scaled NAND Flash Memory
(2012-10-01)
Shirota, Riichiro
;
Huang, Chen-Hao
;
Nagai, Shinji
;
Sakamoto, Yoshinori
;
Li, Fu-Hai
This paper investigates the new programming scheme to reduce the program disturb in the NAND Flash memory. Program disturb characteristics are determined by the unwilling electron injections in the floating gate of the unselected cells during programming. Thus, the key point to improve the program disturb characteristics is how to suppress the electron injection in the unselected cells. This requirement can be implemented by reducing the number of electrons in the unselected NAND strings prior to programming. By applying negative bias to all the word lines in the selected block, excess electrons can be removed from the channel and source/drain regions into the bit line or the source line using drift and diffusion mechanisms, and also electrons in the surface states can be recombined with accumulated holes before programming. After the pretreatment of electron reduction in the NAND string, a normal NAND program sequence follows. The advantage of the pretreatment before programming has been verified by measuring the 8-Gb NAND Flash memory with a 50-nm technology node. Significant reduction of the threshold voltage shift was observed even after the severe program disturb stress, which corresponds to around 30 times of the programming of the 2 bit/cell operation.
Ambient Stability Enhancement of Thin-Film Transistor With InGaZnO Capped With InGaZnO:N Bilayer Stack Channel Layers
(2011-10-01)
Liu, Po-Tsun
;
Chou, Yi-Teh
;
Teng, Li-Feng
;
Li, Fu-Hai
;
Fuh, Chur-Shyang
A thin-film transistor (TFT) with bilayer stack structure of amorphous nitrogenated InGaZnO (IGZO) (a-IGZO:N) on an IGZO channel is proposed to enhance device stability. The a-IGZO: N acting as a back-channel passivation (BCP) is formed sequentially just after the sputter-deposited amorphous IGZO (a-IGZO) film with in situ nitrogen incorporation process. The a-IGZO:N can effectively prevent the a-IGZO channel from exposing to the atmosphere and retarding interactions with ambient oxygen species. Also, the optical energy bandgap of the a-IGZO:N film is decreased due to the addition of nitrogen. This causes the a-IGZO TFT with a-IGZO:N BCP to exhibit high immunity to the ultraviolet-radiation impact.
Characterization of the charge trapping properties in p-channel silicon-oxide-nitride-oxide-silicon memory devices including SiO2/Si3N4 interfacial transition layer
(2015-10-01)
Chiu, Yung-Yueh
;
Yang, Bo-Jun
;
Li, Fu-Hai
;
Chang, Ru-Wei
;
Sun, Wein-Town
The role of SiO2/Si3N4 interfacial transition (IFT) layer in the oxide-nitride-oxide (ONO) tri-layer is quantitatively analyzed for the first time by simulating the temperature and stress-accelerated retention characteristics of p-channel silicon-oxide-nitride-oxide-silicon (SONOS) devices. The ONO tri-layer is modeled as an alloy-dielectric by changing the atomic concentration of silicon, oxygen and nitrogen. It is revealed that simulated results including the IFT layer are more consistent with the experimental data than those neglecting the IFT layer. In addition, the results show that the trapped charge density in IFT layer is two times larger than in the bulk Si3N4 film, due to the oxygen atoms penetrated from SiO2 cause the extrinsic defects in the IFT layer. The energy levels of the trapped charge are continuously distributed, and the peak value is similar to 1.6 eV below the conduction band of the ONO tri-layer with a full width at half maximum of 0.45 eV. (c) 2015 The Japan Society of Applied Physics
Electrical performance and photo-responses enhancement by in situ nitrogen incorporation to amorphous InGaZnO thin-film transistors
(2011)
Teng, Li-Feng
;
Liu, Po-Tsun
;
Fuh, Chur-Shyang
;
Chou, Yi-Teh
;
Li, Fu-Hai
We studied wavelength dependent photo-responses in amorphous nitrogenated InGaZnO thin-film transistors (a-IGZO:N TFTs). The a-IGZO:N active layer was deposited by dc reactive sputter with a nitrogen and argon gas mixture at room temperature and performed the superior characteristics while comparing with the intrinsic IGZO TFTs.
Impact of Source/Drain Junction and Cell Shape on Random Telegraph Noise in NAND Flash Memory
(2013-07-01)
Li, Fu-Hai
;
Shirota, Riichiro
;
傳播研究所
;
電機資訊學士班
;
Institute of Communication Studies
A comprehensive numerical study of threshold voltage fluctuation (Delta V-T) in scaled NAND flash memory caused by random telegraph noise (RTN) and discrete dopant fluctuation (RDF) in both the channel and the cell-to-cell space [source/drain (S/D)] region was carried out. Following a three-dimensional (3D) Monte Carlo (MC) procedure, the statistical distribution of Delta V-T is estimated, considering the effects of both the random placement of discrete doping atoms and a discrete single trap at the tunnel oxide/substrate interface. The result demonstrates the significant influence of the doping in the S/D regions. For the cells with and without an S/D junction, the electron concentration in the S/D region is determined by the pass voltage of the unselected cell (V-pass) and the neighboring cell V-T (V-T(n)), owing to the fringing fields of neighboring floating gates (FGs). As a result, Delta V-T increases in the S/D region as V-pass - V-T(n) decreases. The fluctuation amplitude strongly depends on the [single-trap RTN] position along the cell length (L) and width (W) directions. For the cell shape with rounding of the active area (AA) at the shallow trench isolation (STI) edge, the results indicate that the high Delta V-T area moves from the AA edge towards the center area along the W-direction. (C) 2013 The Japan Society of Applied Physics
Nitrogenated amorphous InGaZnO thin film transistor
(2011-01-31)
Liu, Po-Tsun
;
Chou, Yi-Teh
;
Teng, Li-Feng
;
Li, Fu-Hai
;
Shieh, Han-Ping
This work presents the electrical characteristics of the nitrogenated amorphous InGaZnO thin film transistor (a-IGZO:N TFT). The a-IGZO: N film acting as a channel layer of a thin film transistor (TFT) device was prepared by dc reactive sputter with a nitrogen and argon gas mixture at room temperature. Experimental results show that the in situ nitrogen incorporation to IGZO film can properly adjust the threshold voltage and enhance the ambient stability of a TFT device. Furthermore, the a-IGZO: N TFT has a 44% increase in the carrier mobility and electrical reliability and uniformity also progress obviously while comparing with those not implementing a nitrogen doping process. (C) 2011 American Institute of Physics. [doi:10.1063/1.3551537]
Study Trapped Charge Distribution in P-Channel Silicon-Oxide-Nitride-Oxide-Silicon Memory Device Using Dynamic Programming Scheme
(2013-04-01)
Li, Fu-Hai
;
Chiu, Yung-Yueh
;
Lee, Yen-Hui
;
Chang, Ru-Wei
;
Yang, Bo-Jun
In this study, we precisely investigate the charge distribution in SiN layer by dynamic programming of channel hot hole induced hot electron injection (CHHIHE) in p-channel silicon-oxide-nitride-oxide-silicon (SONOS) memory device. In the dynamic programming scheme, gate voltage is increased as a staircase with fixed step amplitude, which can prohibits the injection of holes in SiN layer. Three-dimensional device simulation is calibrated and is compared with the measured programming characteristics. It is found, for the first time, that the hot electron injection point quickly traverses from drain to source side synchronizing to the expansion of charged area in SiN layer. As a result, the injected charges quickly spread over on the almost whole channel area uniformly during a short programming period, which will afford large tolerance against lateral trapped charge diffusion by baking. (C) 2013 The Japan Society of Applied Physics