Browsing by Author "Li, Gwo-Long"

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135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder
(2013-04-01)
Li, Gwo-Long
;
Chen, Tzu-Yu
;
Shen, Meng-Wei
;
Wen, Meng-Hsun
;
Chang, Tian-Sheuan
To satisfy the video application diversities, an extension of H.264/advanced video coding (AVC), called scalable video coding (SVC), is designed to provide multiple demanded video data via a single video encoder. However, constructed on the fundamental of H.264/AVC, the complexity of SVC is much higher than that of H.264/AVC. In this paper, a VLSI design for all-intra scalable video encoder is proposed to aim at efficient scalable video encoding. First, the memory bandwidth requirements for several encoding methods are analyzed to find out the best encoding method which can achieve best tradeoff between internal memory usage and external memory access. Afterward, an all-intra SVC encoder combined with several advanced techniques, including fast intra prediction algorithm, efficient syntax element encoding approach in context-adaptive variable-length coding, and hardware-efficient techniques, are implemented in a macroblock (MB)-level pipeline to increase data throughput. Implementation results demonstrate that our proposed SVC encoder can process more than 594-k MBs per second, which is equivalent to the summation of 60 high-definition, 1080-p, SD 480-p, and common intermediate format frames under 135-MHz working frequency. The proposed design consumes 258-K gate counts when synthesized by 90-nm CMOS technology.
A 135 MHz 542 k Gates High Throughput H.264/AVC Scalable High Profile Decoder
(2012-04-01)
Li, Gwo-Long
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Chen, Yu-Chen
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Liao, Yuan-Hsin
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Hsu, Po-Yuan
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Wen, Meng-Hsun
To satisfy the requirement of application heterogeneities, the latest H.264/AVC based video coding standard called scalable video coding additional includes temporal, SNR, and spatial scalabilities for frame rate, quality, and frame resolution adaptation. However, these inclusions significantly increase chip design difficulties such as decoding time, memory bandwidth, and area cost. This paper presents an H.264/AVC scalable high profile decoder realization with several optimization techniques to provide high throughput video decoding. For decoding flow, this paper proposes an one-pass macroblock-based quality layer decoding flow for SNR scalability and 71% of external memory bandwidth and 66% of macroblock processing cycles can be saved. For texture padding in interlayer intra prediction, the modified padding flow can save 26% of decoding time. For interlayer predictor design, this paper proposes a centralized concept for accumulation-based calculation of corresponding spatial position, simplified poly-phase interpolator, and efficient motion vector generator to save area cost and decoding time. Furthermore, the residual reconstruction path with the parallelpipeline architecture is also proposed to cope with the additional decoding complexity and thus leads to 54% of gate count savings compared to the traditional serial-pipeline architecture. Finally, the proposed H. 264/AVC scalable high profile decoder design is implemented with 90 nm CMOS technology and it costs 542 k gate count and 39.66 Kbytes on-chip memory while is capable to decode 60 frames/s for CIF+SD480p+HD1080p resolution with three quality layers at 135 MHz operating frequency.
A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video
(2012-11-01)
Liao, Yuan-Hsin
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Li, Gwo-Long
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
To satisfy the heavy performance requirement in real-time high-resolution H.264/AVC, very large-scale integrated implementation of the entropy decoder is necessary since it dominates the overall decoder throughput. In this paper, we propose a high-throughput delay balanced two-level context-based adaptive variable length coding (CAVLC) decoder with 21% shorter critical path delay in comparison to the traditional two-level decoder design. Furthermore, redundant decoding processes are removed by a skipping mechanism. The proposed CAVLC decoder only needs 127.13 cycles per macroblock on average to support level 5.1 decoding with 13.54 k gate counts under 90-nm CMOS technology.
A High Throughput VLSI Design with Hybrid Memory Architecture for H.264/AVC CABAC Decoder
(2010)
Liao, Yuan-Hsin
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Li, Gwo-Long
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A high throughput context-based adaptive binary arithmetic coding (CABAC) decoding design with hybrid memory architecture for H.264/AVC is presented in this paper. To accelerate the decoding speed with hardware cost consideration, a new hybrid memory two-symbol parallel decoding technique is proposed. In addition, an efficient mathematical transform method is also proposed to further decrease the critical path of two-symbol binary arithmetic decoding procedure. The proposed architecture is implemented by UMC 90nm technology and experimental results show that our proposal can operate at 264 MHz with 42.37k gate count, and the throughput is 483.1 Mbins/sec, which surpasses previous design with 48.6% hardware cost saving.
A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder
(2012-02-01)
Liao, Yuan-Hsin
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Li, Gwo-Long
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a high throughput context-based adaptive binary arithmetic coding decoder design is proposed. This decoder employs a syntax element prediction method to solve pipeline hazard problems. It also uses a new hybrid memory two-symbol parallel decoding in order to enhance performance as well as to reduce costs. The critical path delay of the two-symbol binary arithmetic decoding engine is improved by 28% with an efficient mathematical transform. Experimental results show that the throughput of our proposed design can reach 485.76 Mbins/s in the high bit-rate coding and 446.2 Mbins/s on average at 264MHz operating frequency, which is sufficient to support H.264/AVC level 5.1 real-time decoding.
A Memory Efficient Fine Grain Scalability Coefficient Encoding Method for H.264/AVC Scalable Video Extension
(2009)
Shen, Meng-Wei
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Li, Gwo-Long
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a memory efficient Fine Grain Scalability (FGS) coefficient encoding method is proposed to reduce the external memory access requirement. In the H.264/AVC Scalable Video Extension, the FGS coefficients encoding is frame based. However, the frame based mechanism results in the difficulty of hardware implementation due to large internal memory requirements and external memory accesses. Therefore, a non-uniform memory size design which can achieve low external memory access is proposed to realize the macroblock based FGS coefficients encoding. Compared to previous work, our proposed method can save at least 38KB external memory accesses per frame in average.
An Efficient Mode Preselection Algorithm for Fractional Motion Estimation in H.264/AVC Scalable Video Extension
(2013-11-01)
Li, Gwo-Long
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The video coding standard, H.264/AVC scalable video extension (SVC), adopts various advanced interlayer prediction modes to explore the data redundancies between layers for better coding efficiency but at the expense of significantly increased computational complexity and data access bandwidth, especially for hardware realization of fractional motion estimation mode decision. To deal with this problem, this paper proposes a mode preselection algorithm for fractional motion estimation in scalable video coding. We first analyze the rate distortion cost relationship between different prediction modes. With the statistical results, several mode preselection rules are proposed to filter out the potentially skippable prediction modes. Simulation results show that our proposed algorithm reduces up to 65.97% prediction modes and 79.79% coding time on average with only 0.036 dB and 0.496% BD-peak signal-to-noise ratio (PSNR) degradation and BD-rate increase, respectively. Furthermore, the proposed mode preselection algorithm has been implemented in hardware and it costs only 9k gate counts, when synthesized by 90nm CMOS technology.
Bandwidth-Rate-Distortion Optimized Motion Estimation
(2009)
Tai, Wei-Cheng
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Li, Gwo-Long
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Motion estimation process is the most computational and memory intensive component in video encoders. However, traditional motion estimation algorithms focus on rate and distortion performance and do not take memory bandwidth into consideration. As a result, its performance will be degraded under bandwidth constraint environment. In this paper, a bandwidth-rate-distortion optimized motion estimation algorithm is introduced to solve the above issue. Simulation results show that the proposed method could achieve similar performance as the bandwidth unconstrained method with up to 70% bandwidth saving.
Efficient Inter-layer Prediction Hardware Design with Extended Spatial Scalability for H.264/AVC Scalable Extension
(2010)
Chen, Yu-Chen
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Li, Gwo-Long
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
To support inter-layer prediction with arbitrary frame resolution ratio between successive spatial layers, the scalable video coding (SVC) adopts the mechanism of extended spatial scalability (ESS) to achieve it but with noticeable hardware implementation complexity due to the numerous multiplication operations. Therefore, this paper proposes a hardware efficient inter-layer prediction architecture design with ESS by means of accumulator approach. In addition, an area efficient inter-layer interpolator architecture and simplified transform block identification scheme are also proposed to further reduce hardware costs. Simulation results demonstrate that our proposed architecture can significantly save gate count when compared to direct implementation approach.
Memory Analysis for H.264/AVC Scalable Extension Encoder
(2009)
Chen, Tzu-Yu
;
Li, Gwo-Long
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, the first overall memory analysis for H.264/AVC scalable extension (SVC) is presented. Since the dependency among layers is a major discrepancy between SVC and H.264/AVC, the hardware design about them is quite different. Therefore, we analyze the memory bandwidth and memory access requirement of different coding flows for SVC. Based on the analysis results, we deduce that the frame-level method enjoys the best performance. With some improvements from previous work and proposal by our observation, the external memory access could be further reduced by at least 53% than initial design. Furthermore, through our analysis, a solution is provided for the trade-off between internal memory storage and external memory bandwidth in hardware design.
RD Optimized Bandwidth Efficient Motion Estimation and Its Hardware Design with On-Demand Data Access
(2010-11-01)
Li, Gwo-Long
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Data bandwidth dominates the performance and power consumption in the video encoder design. In which a low bandwidth and bandwidth aware motion estimation design enables smooth and better video quality as well as lower power consumption on data accesses. This paper proposes a bandwidth efficient motion estimation and its hardware implementation to deal with the bandwidth issues. First, an on-demand data access mechanism is proposed to acquire the reference data according to the video content for motion estimation process and thus can avoid unnecessary reference data loading. Furthermore, the available bandwidth constraint is properly modeled into our proposed rate distortion optimization framework to efficiently use the data bandwidth. Simulation results show that our proposed algorithm not only allocates proper data bandwidth for motion estimation according to video content but also saves 79.15% data bandwidth demand with 0.03 dB PSNR drop and 2.50% bitrate increase in maximum for 4 CIF resolution sequences, when compared to the fully data reuse full search motion estimation which reuses the overlapped reference data to avoid unnecessary data reloading. In addition, under the available data bandwidth constraint, our proposed algorithm can achieve 2.43%, 0.08%, and 0.20% BD-bitrate saving with 0.17 dB, 0.01 dB, and 0.01 dB BD-PSNR increase on average for high, median, and low motion sequences when compared to the full search motion estimation algorithm. The resulted design only needs 75.27K gate counts when running at 23MHz operating frequency for 4 CIF at 30 frames/s with 90nm CMOS process due to its search range independent buffer design.
RD Optimized Bandwidth Efficient Motion Estimation and Its Hardware Design with On-Demand Data Access
(2010-11-01)
Li, Gwo-Long
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Data bandwidth dominates the performance and power consumption in the video encoder design. In which a low bandwidth and bandwidth aware motion estimation design enables smooth and better video quality as well as lower power consumption on data accesses. This paper proposes a bandwidth efficient motion estimation and its hardware implementation to deal with the bandwidth issues. First, an on-demand data access mechanism is proposed to acquire the reference data according to the video content for motion estimation process and thus can avoid unnecessary reference data loading. Furthermore, the available bandwidth constraint is properly modeled into our proposed rate distortion optimization framework to efficiently use the data bandwidth. Simulation results show that our proposed algorithm not only allocates proper data bandwidth for motion estimation according to video content but also saves 79.15% data bandwidth demand with 0.03 dB PSNR drop and 2.50% bitrate increase in maximum for 4 CIF resolution sequences, when compared to the fully data reuse full search motion estimation which reuses the overlapped reference data to avoid unnecessary data reloading. In addition, under the available data bandwidth constraint, our proposed algorithm can achieve 2.43%, 0.08%, and 0.20% BD-bitrate saving with 0.17 dB, 0.01 dB, and 0.01 dB BD-PSNR increase on average for high, median, and low motion sequences when compared to the full search motion estimation algorithm. The resulted design only needs 75.27K gate counts when running at 23MHz operating frequency for 4 CIF at 30 frames/s with 90nm CMOS process due to its search range independent buffer design.