Browsing by Author "Li, Hung-Wei"

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A low-temperature method for improving the performance of sputter-deposited ZnO thin-film transistors with supercritical fluid
(2009-04-20)
Chen, Min-Chen
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Chang, Ting-Chang
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Huang, Sheng-Yao
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Chang, Kuan-Chang
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Li, Hung-Wei
A low-temperature method, supercritical CO(2) (SCCO(2)) fluid technology, is employed to improve the device properties of ZnO TFT at 150 degrees C. In this work, the undoped ZnO films were deposited by sputter at room temperature and treated by SCCO(2) fluid which is mixed with 5 ml pure H(2)O. After SCCO(2) treatment, the on/off current ratios and threshold voltage of the device were improved significantly. From x-ray photoelectron spectroscopy analyses, the enhancements were attributed to the stronger Zn-O bonds, the hydrogen-related donors, and the reduction in dangling bonds at the grain boundary by OH passivation.
Amorphous Titanium Oxide Semiconductors on Quasi-Crystal-Like InGaZnO Channels for Thin Film Transistor Applications
(2015-06)
Hsu, Hsiao-Hsuan
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Chiou, Ping
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Cheng, Chun-Hu
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Yen, Shiang-Shiou
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Tung, Chien-Hung
This paper reports an InGaZnO thin-film transistor with titanium-oxide semiconductor as channel capping layer. Based on the experimental results, the titanium-oxide semiconductor has the function of not only a surface passivation layer to reduce the defect states localized at grain boundaries near source/drain contacts, but also a mobility booster to enhance electric field across channel. Compared to control IGZO TFT, the crystalline IGZO TFTs with titanium-oxide semiconductor exhibits an improved performance of a low drive voltage of <5 V, a low threshold voltage of 1.9 V, a low sub-threshold swing of 244 mV/decade, and a high mobility of 13.7 cm(2)/V s. The simple titanium-oxide capping process have been demonstrated in this work, which provides considerable potential for further display applications requiring a low power operation and a low-temperature fabrication.
Analysis of Anomalous Capacitance Induced by TAGIDL in p-Channel LTPS TFTs
(2010)
Lin, Chia-Sheng
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Chen, Ying-Chung
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Chang, Ting-Chang
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Li, Hung-Wei
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Chen, Shih-Ching
In this work, a mechanism of anomalous capacitance in p-channel low temperature polycrystalline silicon thin film transistors (LTPS TFTs) was investigated. In general, the effective capacitance of the LTPS TFTs was only dependent with the overlap area between the gate and source/drain under the off-state. However, the experimental results reveal that the off-state capacitance was increased with decreasing measurement frequency and/or with increasing measurement temperature. By fitting the curve of the drain current vs electric field under off-state region, it was verified that the trap-assisted gate-induced drain leakage (TAGIDL) consists of the Pool-Frenkel emission and thermal field emission. In addition, the charge density calculated from the C(gsd)-V(g) measurement also has the same dependence with electric field. This result demonstrates that the anomalous capacitance is mainly due to the TAGIDL. To suppress the anomalous capacitance, a band-to-band hot electron stress was utilized to reduce the vertical electric field between the gate and the drain. The electric field simulation was also performed by TCAD software. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3483759] All rights reserved.
Analysis of Degradation Mechanism in SONOS-TFT Under Hot-Carrier Operation
(2010-12-01)
Chen, Te-Chih
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Chang, Ting-Chang
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Chen, Shih-Ching
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Hsieh, Tien-Yu
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Jian, Fu-Yen
This letter investigates the degradation mechanism of polycrystalline silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon structure under OFF-state stress. During the electrical stress, the hot hole generated from band-to-band tunneling process will inject into gate dielectric, and the significant ON-state degradation (more than 1 order) indicates that the interface states are accompanied with hot-hole injection. In addition, the asymmetric I-V characteristics indicate that the interface states are located near the drain side. Moreover, the ISE-TCAD simulation tool was utilized to model the degradation mechanism and analyze trap states distribution. Although both the vertical and lateral electrical fields are factors for degradation and hot-hole injection, the degradation is mainly affected by the lateral electrical field over a critical point.
Analysis of Electrical Characteristics and Reliability Change of Zinc-Tin-Oxide Thin-Film Transistors by Photo-Thermal Treatment
(2013)
Chen, Yu-Chun
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Chang, Ting-Chang
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Li, Hung-Wei
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Chung, Wan-Fang
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Hsieh, Tien-Yu
This study investigates the influence of a photo-thermal treatment on the electrical characteristics and bias-induced instability of amorphous Zn-Sn-O thin film transistors. Sequences of measurements made in both vacuum and oxygen ambient reveal the most pronounced threshold voltage (V-T) shift, i.e., the highest sensitivity of oxygen, occurs in a device with photo-thermal-treatment. After gate-bias stress in vacuum, the treated device shows less V-T shift than that untreated, which can be attributed to residual adsorbed gas molecules on the backchannel. Thus, the proposed photo-thermal-treatment should be conducted before depositing a passivation layer to increase the reliability of devices after stress. (c) 2013 The Electrochemical Society. All rights reserved.
Anomalous Capacitance Induced by GIDL in P-Channel LTPS TFTs
(2009-11-01)
Lin, Chia-Sheng
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Chen, Ying-Chung
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Chang, Ting-Chang
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Chen, Shih-Ching
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Jian, Fu-Yen
In this letter, a mechanism of anomalous capacitance in p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) was investigated. In general, the effective capacitance was only the overlap region and independent with the frequency in LTPS TFTs under the OFF state. However, our experimental results reveal that the capacitance was related with the leakage current and that it was dependent with the measurement frequencies when operated at the OFF-state region. The increase of the capacitance value is verified to be due to the increase of the electron capacitance originating from a gate-induced drain-leakage (GIDL) one. Nevertheless, the GIDL-induced electron capacitance can be suppressed by employing band-to-band hot electron stress.
Anomalous on-current and subthreshold swing improvement in low-temperature polycrystalline-silicon thin-film transistors under Gate bias stress
(2011-03-21)
Lin, Chia-Sheng
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Chen, Ying-Chung
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Chang, Ting-Chang
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Jian, Fu-Yen
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Li, Hung-Wei
This work investigates an improvement in anomalous on-current and subthreshold swing (SS) in Low-temperature polycrystalline-silicon thin-film transistors after positive gate bias stress. The experimental results reveal that the improved electric properties are due to the hole trapping at SiO(2) above the lightly doped drain regions, which causes a strong electric field at the gate corners. The effect of the hole trapping is to reduce the effective channel length and the SS. Besides, the stress-related electric field was also simulated by TCAD software to verify the mechanism above. (C) 2011 American Institute of Physics. [doi:10.1063/1.3568895]
Bias-induced oxygen adsorption in zinc tin oxide thin film transistors under dynamic stress
(2010-06-28)
Chen, Yu-Chun
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Chang, Ting-Chang
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Li, Hung-Wei
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Chen, Shih-Ching
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Lu, Jin
This study investigates the effects of bias-induced oxygen adsorption on the electrical characteristic instability of zinc tin oxide thin film transistors in different ambient oxygen partial pressures. When oxygen pressure is largest, the threshold voltages showed the quickest increase but the slowest recovery during the stress phase and recovery phase, respectively. This finding corresponds to the charge trapping time constant and recovery time constant, which are extracted by fitting the stretched-exponential equation and which exhibit a relationship with oxygen pressure. We suggest that the gate bias reduces the activation energy of oxygen adsorption during gate bias stress. (C) 2010 American Institute of Physics. [doi: 10.1063/1.3457996]
Carrier Transport and Multilevel Switching Mechanism for Chromium Oxide Resistive Random-Access Memory
(2011)
Chen, Shih-Cheng
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Chang, Ting-Chang
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Chen, Shih-Yang
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Li, Hung-Wei
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Tsai, Yu-Ting
This article investigates the carrier transport phenomenon and multilevel switching mechanism of Cr(2)O(3)-based resistive random access memory (RRAM) with Pt/Cr(2)O(3)/TiN structure. Before the forming process, the interfacial Schottky barrier dominates the carrier transport. The barrier heights of Pt/Cr(2)O(3) and Cr(2)O(3)/TiN are 0.7 and 0.96 eV, respectively. After the forming process, RRAM at a low resistance state follows the Ohmic conduction. While RRAM is switched to a high resistance state during the reset process, the Frenkel-Poole emission becomes a dominant conduction mechanism. The multilevel resistance states were achieved by applying corresponding reset voltages to the device for controlling the trap levels of the Cr(2)O(3) layer. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3518710] All rights reserved.
Characterization of environment-dependent hysteresis in indium gallium zinc oxide thin film transistors
(2013-09-01)
Chen, Yu-Chun
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Chang, Ting-Chang
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Li, Hung-Wei
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Chung, Wan-Fang
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Chen, Shih-Cheng
This study investigates environmentally dependent electrical performance as a function of hysteresis phenomena for amorphous indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs). Because ambient gas has a great influence on the electrical characteristics of zinc oxide-based TFTs during electrical measurements, the hysteresis for current-voltage and capacitance-voltage measurements are employed in different ambient gases (ambient air, vacuum, oxygen ambient and moisture ambient) to study this issue. Although the hysteresis phenomenon has been explained by the charge trapping and de-trapping model, in order to obtain stable electrical characteristics it is necessary to clarify the original principal mechanism leading to threshold voltage instability under gate bias operations in different environments. Also, the relationship between de-trapping rate and electrical hysteresis is investigated by prolonging the integration time of the semiconductor parameter analyzer. This study may be of importance in explaining the dynamic relationship between the TFT electrical characteristics and ambient gas, as well as providing a better understanding of the environment-dependent hysteresis phenomenon of the IGZO TFTs. (C) 2012 Elsevier B.V. All rights reserved.
Charge-Trapping-Induced Parasitic Capacitance and Resistance in SONOS TFTs Under Gate Bias Stress
(2011-03-01)
Lin, Chia-Sheng
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Chen, Ying-Chung
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Chang, Ting-Chang
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Jian, Fu-Yen
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Li, Hung-Wei
This letter investigates the charge-trapping-induced parasitic resistance and capacitance in silicon-oxide-nitride-oxide-silicon thin-film transistors under positive and negative dc bias stresses. The results identify a parasitic capacitance in OFF-state C-V curve caused by electrons trapped in the gate insulator near the defined gate region during the positive stress, as well as the depletion induced by those trapped electrons. Meanwhile, the induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.
Degradation of Low Temperature Polycrystalline Silicon Thin Film Transistors under Negative Bias Temperature Instability Stress with Illumination Effect
(2010)
Lin, Chia-Sheng
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Chen, Ying-Chung
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Chang, Ting-Chang
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Li, Hung-Wei
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Hsu, Wei-Che
This work investigates negative bias temperature instability (NBTI) in low temperature polycrystalline silicon thin film transistors (LTPS TFTs) in a darkened and in an illuminated environment of different light intensities. Experimental results reveal that the generations of interface state density (N(it)) are identical under various illuminated intensity NBTI stresses. Nevertheless, the degradation of the grain boundary trap (N(trap)) under illumination was more significant than that for the darkened environment, with degradation increasing as illumination intensity increases. This phenomenon is mainly caused by the extra number of holes generated during the illuminated NBTI stress. The increased N(trap) degradation leads to an increase in the darkened environment leakage current. This indicates that more traps are generated in the drain junction region than from carrier tunneling via the trap, resulting in leakage current. Conversely, an increase in N(trap) degradation results in a decrease in the photoleakage current. This indicates that the number of recombination centers increases in the poly-Si bulk, affecting photosensitivity in LTPS TFTs.
Dependence of Light-Accelerated Instability on Bias and Environment in Amorphous Indium-Gallium-Zinc-Oxide Thin Film Transistors
(2013)
Chen, Yu-Chun
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Chang, Ting-Chang
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Li, Hung-Wei
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Chung, Wan-Fang
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Hsieh, Tien-Yu
This study examines the dependence of light-accelerated instability on bias and environment in amorphous indium-gallium-zinc-oxide thin film transistors. When device is in vacuum ambient, the threshold voltage of device after negative gate bias illumination stress (NBIS) showed bias-dependent electrical degradation behavior. However, experimental results show the degradation of electrical characteristic in a-IGZO devices does not only rely on the charge trapping mechanism for NBIS. During NBIS in oxygen, moisture-simulated and atmosphere ambient, the negative shift in electrical characteristic is suppressed when compared to that in vacuum. This implies that the adsorbent gas species in the surrounding environment dominates the electrical characteristic degradation of devices during NBIS, which leading the change of dominant mechanism from photon-created carrier trapping to adsorbed/desorbed gas phenomenon. (C) 2013 The Electrochemical Society. All rights reserved.
Effect of Lateral Body Terminal on Silicon-Oxide-Nitride-Oxide-Silicon Thin-Film Transistors
(2011-10-01)
Li, Hung-Wei
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Chang, Ting-Chang
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Chang, Geng-Wei
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Lin, Chia-Sheng
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Tsai, Tsung-Ming
We investigate lateral-body-terminal silicon-oxide-nitride-oxide-silicon thin-film transistors (LBT SONOS TFTs) under erasing operation. These devices have superior erasing efficiency by gate as well as lateral body electrode exerting bias. The erasing mechanism of LBT SONOS TFTs has been illustrated by the energy band diagrams. Holes gain sufficient energy by the electric field in the deep-depletion region to surmount the tunneling oxide barrier because of exerting body bias under erasing operation. In addition, the lateral body terminal exerting bias can enhance the erasing efficiency and is confirmed by different erasing conditions and structures. In addition, to verify the hole current injecting from the lateral body site, the size effect of LBT SONOS TFTs is also discussed.
Effect of SiO2 Buffer Layer Thickness on Performance and Reliability of Flexible Polycrystalline Silicon TFTs Fabricated on Polyimide
(2016-12-01)
Chen, Bo-Wei
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Chang, Ting-Chang
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Hung, Yu-Ju
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Huang, Shin-Ping
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Chen, Hua-Mao
This letter investigates flexible polycrystalline silicon thin film transistor performance variation due to different buffer layer thicknesses. In flexible electronics, thermal expansion stress during device fabrication is inevitable. A thicker SiO2 buffer demonstrates better endurance to thermal expansion stress from the polyimide substrate during device annealing. However, if the SiO2 buffer thickness is above a critical point, its weak heat dissipation capability causes the optimal ELA crystallization condition to shift. A thermal expansion stress simulation and TEM photos were utilized to verify performance variation. Furthermore, a similar trend was observed in electrical characteristics after negative bias temperature instability.
Effects of Post-Deposition Annealing Atmosphere and Duration on Sol-Gel Derived Amorphous Indium-Zinc-Oxide Thin Film Transistors
(2011)
Chung, Wan-Fang
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Chang, Ting-Chang
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Li, Hung-Wei
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Tseng, Tseung-Yuen
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Tai, Ya-Hsiang
This work shows the effects of post-deposition annealing atmosphere and duration on the properties of sol-gel derived amorphous indium zinc oxide thin film transistors (a-IZO TFTs). Two different post-deposition annealing atmospheres, nitrogen and oxygen, were used in this study. Experimental results showed that the O-2-annealed devices showed better electrical characteristics than the N-2-annealed samples. Under O-2-annealing, field effect mobility was enhanced to 1.47 cm(2)/V s, the threshold voltage increased to -4.61 V and the subthreshold swing improved to 0.86 V/dec. Also, the transfer characteristics of a-IZO TFTs improve with annealing time. X-ray photoelectron spectroscopy (XPS) analysis indicated that the chemical composition of the IZO film was modified by the oxygen annealing.
Elimination of photoleakage current in poly-Si TFTs using a metal-shielding structure
(2008)
Lu, Hau-Yan
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Chang, Ting-Chang
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Liu, Po-Tsun
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Li, Hung-Wei
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Hu, Chin-Wei
A technology to eliminate the photoleakage current of poly-Si thin-film transistors (TFTs) with top gate structure has been developed. A thin metal film is formed on the glass substrate to be used as a light-shielding layer. The light-shielding layer, buffer layer, and active island are patterned employing the same mask. The leakage current and the variation of subthreshold swing in the proposed devices are suppressed completely under illumination. Due to the parasitic capacitance in the overlap region between the drain side and the metal-shielding layer, a floating voltage coupled from drain bias influences the threshold voltage of the proposed poly-Si TFTs. (c) 2008 The Electrochemical Society.
Environment-dependent thermal instability of sol-gel derived amorphous indium-gallium-zinc-oxide thin film transistors
(2011-04-11)
Chung, Wan-Fang
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Chang, Ting-Chang
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Li, Hung-Wei
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Chen, Shih-Ching
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Chen, Yu-Chun
The environment-dependent electrical performances as a function of temperature for sol-gel derived amorphous indium-gallium-zinc-oxide (a-IGZO) thin film transistors are investigated in this letter. In the ambients without oxygen, thermal activation dominates and enhances device performance. In oxygen-containing environments, mobility and drain current degrades and the threshold slightly increase as temperature increases. We develop a porous model for a-IGZO film relating to the drain current and mobility lowering due to film porosity and oxygen adsorption/penetration. It also relates to the threshold voltage recovery at high temperature owing to the varying form of adsorbed oxygen and the combination of oxygen and vacancies. (C) 2011 American Institute of Physics. [doi:10.1063/1.3580614]
Formation and nonvolatile memory characteristics of W nanocrystals by in-situ steam generation oxidation
(2010-12-30)
Chen, Shih-Cheng
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Chang, Ting-Chang
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Hsieh, Chieh-Ming
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Li, Hung-Wei
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Sze, S. M.
The authors provide the formation and memory effects of W nanocrystals nonvolatile memory in this study. The charge trapping layer of stacked a-Si and WSi(2) was deposited by low pressure chemical vapor deposition (LPCVD) and was oxidized by in-situ steam generation system to form uniform W nanocrystals embedded in SiO(2). Transmission electron microscopy analyses revealed the microstructure in the thin film and X-ray photon-emission spectra indicated the variation of chemical composition under different oxidizing conditions. Electrical measurement analyses showed the different charge storage effects because the different oxidizing conditions influence composition of trapping layer and surrounding oxide quality. Moreover, the data retention and endurance characteristics of the formed W nanocrystal memory devices were compared and studied. The results show that the reliability of the structure with 2% hydrogen and 98% oxygen at 950 degrees C oxidizing condition has the best performance among the samples. (C) 2010 Elsevier B.V. All rights reserved.
H(2)O-Assisted O(2) Adsorption in Sol-Gel Derived Amorphous Indium Gallium Zinc Oxide Thin Film Transistors
(2011-01-01)
Chung, Wan-Fang
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Chang, Ting-Chang
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Li, Hung-Wei
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Chen, Shih-Ching
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Chen, Yu-Chun
This paper investigates the environmental effects and related adsorbent species reactions on sol-gel derived amorphous indium gallium zinc oxide thin film transistors (a-IGZO TFTs). The discrepancy between device characteristics measured in atmospheric and vacuum conditions was clarified through experiments with thermal annealing and different gas partial pressures. The measurement of a-IGZO TFTs in simulated water vapor environment was also utilized. We verified that the adsorbed water originating from the surrounding atmosphere can cause an increase in off-current and also enhance more oxygen molecule adsorption on the exposed back-channel surface, leading to more serious degradation in on-current. (C) 2011 The Electrochemical Society. [DOI: 10.1149/1.3568831] All rights reserved.