Browsing by Author "Li, Kai-Shin"

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A Numerical Study of Si-TMD Contact with n/p Type Operation and Interface Barrier Reduction for Sub-5 nm Monolayer MoS2 FET
(2016-01-01)
Tang, Ying-Tsan
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Li, Kai-Shin
;
Li, Lain-Jong
;
Li, Ming-Yang
;
Lin, Chang-Hsien
An atomic-scale numerical study of Si contact with transition metal dichalcogenides (TMD) semiconductor materials is proposed by first-principles simulation for the first time. The monolayer MoS2 channel can be operated as both of n- and p-type FET by properly doping Si S/D to adjust the TMD channel potential. The gradient MoSx junction of dichalcogenide vacancies enables Si-MoS2 contact resistance lower than 100 Omega-mu m for interface Schottky barrier height reduction. The compact Si-MoS2 interface study can potentially provide monolayer TMD contact design guideline for the sub-5 nm TMD FET fabrication technology.
Analytical Modeling of Read-Induced SET-State Conductance Change in a Hafnium-Oxide Resistive Switching Device
(2020-01-01)
Su, Po-Cheng
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Jiang, Cheng-Min
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Chen, Yu-Jia
;
Wang, Chih-Chieh
;
Li, Kai-Shin
A SET-state conductance change in a hafnium-oxide resistive switching memory cell due to repeated read events is investigated. We characterize a read-induced conductance change at different read voltages and SET-state conductance levels. Our result shows that the read-induced conductance degradation exhibits a two-stage evolution with the read pulse number. A SET-state conductance decreases slightly in the first stage and then follows inverse power-law dependence on the read number in the second stage. The power factor is an exponential function of a read voltage without regard to the SET-state conductance level, and the read pulse number at the transition of the two stages is related to a read voltage and conductance level. An analytical model to describe the two-stage conductance evolution is proposed. The parameters in the model are extracted from measurement data. Our model is verified by good agreement between the modeled and measured results in a wide range of read pulse number, read voltage, and SET-state conductance level.
Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiOx/Si Substrates Using Area-Selective CVD Technology
(2019-12-01)
Chung, Yun-Yan
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Lu, Kuan-Cheng
;
Cheng, Chao-Ching
;
Li, Ming-Yang
;
Lin, Chao-Ting
For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have successfully grown continuous and uniform WS2 film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the transmission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS2 channels on SiOx/Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 10(6), a subthreshold swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL).
Effective N-methyl-2-pyrrolidone wet cleaning for fabricating high-performance monolayer MoS2 transistors
(2019-02-01)
Chen, Po-Chun
;
Lin, Chih-Pin
;
Hong, Chuan-Jie
;
Yang, Chih-Hao
;
Lin, Yun-Yan
Two-dimensional semiconductors, such as MoS2 are known to be highly susceptible to diverse molecular adsorbates on the surface during fabrication, which could adversely affect device performance. To ensure high device yield, uniformity and performance, the semiconductor industry has long employed wet chemical cleaning strategies to remove undesirable surface contaminations, adsorbates, and native oxides from the surface of Si wafers. A similarly effective surface cleaning technique for two-dimensional materials has not yet been fully developed. In this study, we propose a wet chemical cleaning strategy for MoS2 by using N-methyl-2-pyrrolidone. The cleaning process not only preserves the intrinsic properties of monolayer MoS2, but also significantly improves the performance of monolayer MoS2 field-effect-transistors. Superior device on current of 12 Am-1 for a channel length of 400 nm, contact resistance of 15 km, field-effect mobility of 15.5 cm(2)V(-1)s(-1), and the average on-off current ratio of 10(8) were successfully demonstrated
First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrate
(2019-01-01)
Cheng, Chao-Ching
;
Chung, Yun-Yan
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Li, Ming-Yang
;
Lin, Chao-Ting
;
Li, Chi-Feng
Area-selective channel material growth for 2D transistors is more desirable for volume manufacturing than exfoliation or wet/dry transfer after large area growth. We demonstrate the first top-gate WS(2)p-channel field-effect transistors (p-FETs) fabricated on SiOx/Si substrate using channel area-selective CVD growth. Smooth and uniform WS2 comprising approximately 6 layers was formed by area-selective CVD growth in which a patterned tungsten-source/drain served as the seed for WS2 growth. For a 40 nm gate length transistor, the device has impressive electrical characteristics: on/off ratio of similar to 10(6), a S.S. of similar to 97 mV/dec.. and nearly zero DIBL.
First Fully Functionalized Monolithic 3D(+) IoT Chip with 0.5 V Light-electricity Power Management, 6.8 GHz Wireless-communication VCO, and 4-layer Vertical ReRAM
(2016-01-01)
Hsueh, Fu-Kuo
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Shen, Chang-Hong
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Shieh, Jia-Min
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Li, Kai-Shin
;
Chen, Hsiu-Chih
For the first time, we report low-cost heterogeneously integrated sub-40nm epi-like Si monolithic internet of thins (IoT) 3D(+)-IC with wireless communication, light-electricity power management and vertical ReRAM (VRRAM) modules. High current driving multi-channel 3D(+) UTB-MOSFETs (600 mu A/282 mu A@V-G = +/- 1V for 10-channel P/N FETs) was fabricated by low thermal budget super-CMP-planarized visible laser-crystallized epi-like Si channel and CO2 far-infrared laser annealing (CO2-FIR-LA) activation technologies that support a 6.8GHz high frequency VCO circuits, 0.5V low-voltage power management circuit and drives 20nm 4-layer VRRAM (Set/Reset <1.2V/1.8V, 3-bits/cell). This unique TSV-free monolithic 3D(+)IC process provides the superiority in 3D hetero-integration; we successfully integrate these circuits in a low cost, small footprint, fully functionalized 3D(+) IoT chip.
Improvement of ferroelectric properties in undoped hafnium oxide thin films using thermal atomic layer deposition
(2019-06-01)
Luo, Jun-Dao
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Zhang, He-Xin
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Wang, Zheng-Ying
;
Gu, Siang-Sheng
;
Yeh, Yun-Tien
Modulating the water pulse time during thermal atomic layer deposition is an effective approach to enhancing the ferroelectric properties of undoped HfO2 thin films. Through grazing incidence X-ray diffraction (GI-XRD), it was observed that a shorter water pulse time can inhibit formation of the monoclinic phase and thereby obtain good remanent polarization. Transmission electron microscopy (TEM) images and GIXRD analysis were used to reveal the crystallization conditions of the undoped HfO2 thin films. By modulating the water pulse time during deposition of all samples, no impurities were found in these films via X-ray photoelectron spectroscopy. Moreover, samples with shorter water pulse times revealed lower binding energy and higher leakage current. However, electric measurement results of samples with shorter water pulse times revealed a higher remanent polarization of approximately 9 mu C cm(-2) and a coercive field of similar to 1.95 MV cm(-1) compared with other samples. After endurance testing, the films lasted for more than 10(8) cycles at 2.25 V, so they are ideally suited to low-power ferroelectric CMOS devices and nonvolatile memory applications. (c) 2019 The Japan Society of Applied Physics
Monolithic 3D SRAM-CIM Macro Fabricated with BEOL Gate-All-Around MOSFETs
(2019-01-01)
Hsueh, Fu-Kuo
;
Lee, Chun-Ying
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Xue, Cheng-Xin
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Shen, Chang-Hong
;
Shieh, Jia-Min
For the first time, below 400 degrees C-fabricated gate-all-around (GAA) transistor fabrication process was demonstrated with monolithic computing-in-memory (CIM) circuit. Key enablers are plasma-assisted atomic layer etching (PA-ALE), plasma immersion ion implantation (PIII) and far-infrared laser activation (FIR-LA). The 3D stackable single-grained Si GAA MOSFETs thus fabricated exhibit record-high I-on/I-off ratio (similar to 10(8)) with low I-off (pFETs<10(-2) nA/mu m). Moreover, the stackability of the GAA MOSFETs and the differential output of dual-mode 10T SRAM readout enable 2x throughput in the CIM circuitry.
MOS2 U-shape MOSFET with 10 nm Channel Length and Poly-Si Source/Drain Serving as Seed for Full Wafer CVD MOS2 Availability
(2016)
Li, Kai-Shin
;
Wu, Bo-Wei
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Li, Lain-Jong
;
Li, Ming-Yang
;
Cheng, Chia-Chin Kevin
A U-shape MOS2 pMOSFET with 10nm channel and poly-Si source/drain is demonstrated. The fabrication process is simple. Because the Si S/D serves as the nucleation seed for CVD MOS2 deposition, thin MOS2 is well deposited in the channel region any where over the fully scale oxide coated Si wafer. This is a big step forward toward a low cost multi-layer stacked TMD IC technology.
Negative-Capacitance FinFET Inverter, Ring Oscillator, SRAM Cell, and Ft
(2018-01-01)
Li, Kai-Shin
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Wei, Yun-Jie
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Chen, Yi-Ju
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Chiu, Wen-Cheng
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Chen, Hsiu-Chih
In this work, we use thermal-ALD to prepare ferroelectric HfZrO2 (HZO) thin film with thickness from 3 to 7 nm for the NC-FinFET's gate stack. The subthreshold swing (SS) was as low as 5 mV/dec (SSmin) over 4 orders of I-D. Lower thermal budget process, CO2 far-infrared laser activation and 400 degrees C Ni silicide are employed in the 2-level metal backend integration for maintaining the orthorhombic phase in HZO thin film and minimizing the hysteresis in IV. NC-FinFET inverter has 77% higher voltage gain compared to FinFET-inverter employing HfO2 gate dielectric. NC-FinFET ring oscillator exhibit small speed and power advantages over FinFET oscillator. For the first time, NC-FET cut-off frequency (F-t) frequency is measured, 23.1 GHz or 23% higher than the control FET Ft. NC-FinFET SRAM was observed to exhibit large noise margin.
Nonvolatile molecular memory with the multilevel states based on MoS2 nanochannel field effect transistor through tuning gate voltage to control molecular configurations
(2020-04-17)
Lan, Yann-Wen
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Hong, Chuan-Jie
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Chen, Po-Chun
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Lin, Yun-Yan
;
Yang, Chih-Hao
A new flexible memory element is crucial for mobile and wearable electronics. A new concept for memory operation and innovative device structure with new materials is certainly required to address the bottleneck of memory applications now and in the future. We report a new nonvolatile molecular memory with a new operating mechanism based on two-dimensional (2D) material nanochannel field-effect transistors (FETs). The smallest channel length for our 2D material nanochannel FETs was approximately 30 nm. The modified molecular configuration for charge induced in the nanochannel of the MoS2 FET can be tuned by applying an up-gate voltage pulse, which can vary the channel conductance to exhibit memory states. Through controlling the amounts of triggered molecules through either different gate voltage pulses or gate duration time, multilevel states were obtained in the molecular memory. These new molecular memory transistors exhibited an erase/program ratio of more than three orders of current magnitude and high sensitivity, of a few picoamperes, at the current level. Reproducible operation and four-level states with stable retention and endurance were achieved. We believe this prototype device has potential for use in future memory devices.
Superconductivity-induced magnetoresistance suppression in hybrid superconductor/magnetic tunnel junctions
(2009-01-01)
Chang, Yin-Ming
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Li, Kai-Shin
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Chiang, Wen-Chung
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Lin, Jiunn-Yuan
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Lin, Minn-Tsong
Hybrid superconductor/magnetic tunnel junctions of Nb/CoFe/AlO/CoFe/NiFe have been implemented to investigate the impact of the superconducting Nb layer on the proximal ferromagnetic CoFe layer. A suppression of tunneling magnetoresistance effect is observed as the Nb layer undergoes the superconducting transition. This suppression is thought to be due primarily to the coupling of the magnetic inhomogeneity of CoFe to the superconductivity of Nb. The magnetic structure-vortex interactions interplay each other, inducing a complex domain evolution in the magnetization process and consequently degrading the junction's antiparallel magnetization alignment.
TMD FinFET with 4 nm Thin Body and Back Gate Control for Future Low Power Technology
(2015)
Chen, Min-Cheng
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Li, Kai-Shin
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Li, Lain-Jong
;
Lu, Ang-Yu
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Li, Ming-Yang
A 4 nm thin transition-metal dichalcogenide (TMD) body FinFET with back gate control is proposed and demonstrated for the first time. The TMD FinFET channel is deposited by CVD. Hydrogen plasma treatment of TMD is employed to lower the series resistance for the first time. The 2 nm thin back gate oxide enables 0.5 V of Vth shift with 1.2 V change in back bias for correcting device variations and dynamically configuring a device as a high performance or low leakage device. TMD can potentially provide sub-nm thin monolayer body needed for 2 nm node FinFET.