Browsing by Author "Li, Katherine Shu-Min"

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A Layout-Aware Test Methodology for Silicon Interposer in 3D System-in-a-Package
(2013)
Gu, Ruei-Ting
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Ho, Cheng-You
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Li, Katherine Shu-Min
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Ho, Yingchieh
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Chen, Liang-Bi
In this paper, we propose an efficient silicon interposer pre-test methodology, which is based on the layout-aware ripple baseline algorithm for System-in-a-Package (SiP). The proposed methodology uses FPGA as our test vehicle that can test all interconnects at once without any test probes. The test interposer is synthesized according to the given layout of the target interposers, which provide microbumps and solder balls with pitches, and the test interposers are connected to the upper test side of the target interposers. Thus the test loops, which cover all interconnections of the target interposers, are built by connecting the test interposers and the target interposers. The bottom side of the target interposer is connected to an FPGA as the tester that provides test patterns to the target interposer and compares the result to identify the faulty interconnections of the target interposer. Experimental results show our method is both effective and efficient with achieving 100% fault coverage for all interposers. With scaling to more than hundreds of hundreds interposers, our method is still effective within two to three hours.
A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus
(2009-02-01)
Li, Katherine Shu-Min
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Lee, Chung-Len
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Su, Chauchin
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Chen, Jwu E.
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電子工程學系及電子研究所
For very deep sub-micrometer VLSI, crosstalk becomes an important issue in affecting performance and signal integrity of the circuits. Two crosstalk fault effects, namely, glitch and crosstalk-induced delay, in the system-on-chip (SOC) interconnect bus are analyzed and a unified scheme to detect them is proposed and demonstrated in this paper. The crosstalk induced delay is found to be superposition of the induced glitch and the applied signal at the victim line, and this effect is more important in affecting the circuit performance. A pulse detector with an adjustable detection threshold is proposed to detect glitches and consequently the induced delay. Several issues affecting the yield of the proposed testing scheme are discussed and Monte Carlo simulations are conducted to show the feasibility of the scheme.
Co-placement optimization in sensor-reusable cyber-physical digital microfluidic biochips
(2019-01-01)
Li, Jian-De
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Kuo, Chun-Hao
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Lu, Guan-Ruei
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Wang, Sying-Jyan
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Li, Katherine Shu-Min
Digital microfluidic biochips (DMFBs) facilitate modern healthcare applications. One of the most important applications is point-of-care (POC) clinical diagnosis which is directly related to human health. However, biochemical experiments are usually error-prone, which makes monitoring intermediate results during bioassay execution be required to ensure the correctness of POC clinical diagnosis. To tackle this problem, cyber-physical digital microfluidic biochips with integrated sensors have been proposed and have attracted attention recently. In order to fully utilize the sensors for detection, the reusability of sensors should be taken into consideration during the module placement stage of cyber-physical DMFBs synthesis flow. Moreover, excessive actuation of electrodes may cause reliability degradation and this issuse should also be taken care of during module placement stage. In order to deal with the aforementioned problems, this paper presents the first co-optimization method for both module and sensor placement. Experimental results show that the proposed method can effectively minimize bioassay completion time while meeting all constraints from sensors and electrodes.
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults
(2006-11-01)
Li, Katherine Shu-Min
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Su, Chauchin
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Chang, Yao-Wen
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Lee, Chung-Len
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Chen, Jwu E.
An interconnect diagnosis scheme based on the oscillation ring (OR) test methodology for systems-on-chip (SOC) design with heterogeneous cores is proposed. In addition to traditional stuck-at and open faults, the OR test can also detect and diagnose important interconnect faults such as delay faults and crosstalk glitches. The large number of test rings in the SOC design, however, significantly complicates the interconnect diagnosis problem. In this paper, the diagnosability of an interconnect structure is first analyzed then a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm are proposed. It is shown in this paper that the generation algorithm achieves the maximum diagnosability for any interconnect. Two optimization techniques are also proposed, an adaptive and a concurrent diagnosis method, to improve the efficiency and effectiveness of interconnect diagnosis. Experiments on the MCNC benchmark circuits show the effectiveness of the proposed diagnosis algorithms. In all experiments, the method achieves 100% fault detection coverage and the optimal interconnect diagnosis resolution.
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults
(2006-01-01)
Li, Katherine Shu-Min
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Chang, Yao-Wen
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Su, Chauchin
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Lee, Chung-Len
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Chen, Jwu E.
We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and crosstalk glitches. We analyze the diagnosability of an interconnect structure and propose a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm which achieves the optimal diagnosability. Two optimization techniques improve the efficiency and effectiveness of interconnect diagnosis. In all experiments, our method achieves 100% fault coverage and the optimal diagnosis resolution.
IEEE standard 1500 compatible oscillation ring test methodology for interconnect delay and crosstalk detection
(2007-08-01)
Li, Katherine Shu-Min
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Lee, Chung-Len
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Su, Chauchin
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Chen, Jwu E.
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電子工程學系及電子研究所
A novel oscillation ring (OR) test scheme and architecture for testing interconnects in SOC is proposed and demonstrated. In addition to stuck-at and open faults, this scheme can also detect delay faults and crosstalk glitches, which are otherwise very difficult to be tested under the traditional test schemes. IEEE Std. 1500 wrapper cells are modified to accommodate the test scheme. An efficient algorithm is proposed to construct ORs for SOC based on a graph model. Experimental results on MCNC benchmark circuits have been included to show the effectiveness of the algorithm. In all experiments, the scheme achieves 100% fault coverage with a small number of tests.
Multilevel full-chip routing with testability and yield enhancement
(2007-09-01)
Li, Katherine Shu-Min
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Chang, Yao-Wen
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Lee, Chung-Len
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Sul, Chauchin
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Chen, Jwu E.
We propose a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two major issues are addressed. 1) The oscillation ring test (ORT) and its diagnosis scheme for interconnects based on the popular IEEE Standard 1500 are integrated into the multilevel routing framework to achieve testability enhancement. We augment the traditional multilevel framework of coarsening and uncoarsening by introducing a preprocessing stage that analyzes the interconnect structure for better resource estimation before the coarsening stage, and a final stage after uncoarsening that improves testability to achieve 100% interconnect fault coverage and maximal diagnosability. 2) We present a heuristic to reduce routing congestion to optimize the multiple-fault probability, chemical-mechanical polishing- and optical proximity correction-induced manufacturability, and crosstalk effects, for yield improvement. Experimental results on the Microelectronics Center for North Carolina benchmark circuits show that the proposed ORT method achieves 100% fault coverage and the optimal diagnosis resolution for interconnects. Further, the multilevel routing algorithm effectively balances the routing density to achieve 100% routing completion.
Oscillation ring based interconnect test scheme for SOC
(2005)
Li, Katherine Shu-Min
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Lee, Chung Len
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Su, Chauchin
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Chen, Jwu E.
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電子工程學系及電子研究所
We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and crosstalk glitches. IEEE P1500 wrapper cells are modified. An efficient ring-generation algorithm is proposed to construct ORs based on a graph model. Experimental results on MCNC benchmark circuits show the feasibility of the scheme and the effectiveness of the algorithm. Our method achieves 100% fault coverage with a small number of tests.