Browsing by Author "Li, M. -F."

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Flat band voltage control on low V(t) metal-gate/high-kappa CMOSFETs with small EOT
(2009-07-01)
Chin, Albert
;
Chang, M. F.
;
Lin, S. H.
;
Chen, W. B.
;
Lee, P. T.
The unwanted high threshold voltage (V(t)) is the major challenge for metal-gate/high-kappa CMOs especially at small equivalent-oxide-thickness (EOT). We have investigated the high V(t) issue that is due to flat-band voltage (V(fb)) roll-off at smaller EOT. A mechanism of charged oxygen vacancies formed by interface reaction was proposed to explain the V(fb) roll-off effect. This interface reaction can be decreased by inserting a thin interfacial SiON and using novel low temperature process. The self-aligned and gate-first metal-gate/high-kappa CMCSFETs using these methods have achieved low V(t) and good control of V(fb) roll-off at small 0.6-1.2 nm EOT. Crown Copyright (C) 2009 Published by Elsevier B.V. All rights reserved,
Flat band voltage control on low V-t metal-gate/high-kappa CMOSFETs with small EOT
(2009-07-01)
Chin, Albert
;
Chang, M. F.
;
Lin, S. H.
;
Chen, W. B.
;
Lee, P. T.
The unwanted high threshold voltage (V-t) is the major challenge for metal-gate/high-kappa CMOs especially at small equivalent-oxide-thickness (EOT). We have investigated the high V-t issue that is due to flat-band voltage (V-fb) roll-off at smaller EOT. A mechanism of charged oxygen vacancies formed by interface reaction was proposed to explain the V-fb roll-off effect. This interface reaction can be decreased by inserting a thin interfacial SiON and using novel low temperature process. The self-aligned and gate-first metal-gate/high-kappa CMCSFETs using these methods have achieved low V-t and good control of V-fb roll-off at small 0.6-1.2 nm EOT. Crown Copyright (C) 2009 Published by Elsevier B.V. All rights reserved,
High temperature stable [Ir3Si-TaN]/HfLaON CMOS with large work-function difference
(2006)
Wu, C. H.
;
Hung, B. F.
;
Chin, Albert
;
Wang, S. J.
;
Chen, W. J.
We report novel 1000 degrees C-stable [Ir3Si-TaN]/HfLaON CMOS for the first time, where the self-aligned and gate-first process are full compatible to current VLSI. Good phi(m.eff) of 5.08 and 4.24 eV, low V, of -0.10 and 0.18 V, high mobility of 84 and 217 cm(2)/Vs at 1.6 nm EOT, and small 850 degrees C BTI < 20 mV (10 MV/cm for 1 hr) are measured.
High-temperature stable HfLaON p-MOSFETs with high-work-function Ir3Si gate
(2007-04-01)
Wu, C. H.
;
Hung, B. F.
;
Chin, Albert
;
Wang, S. J.
;
Wang, X. P.
We report a novel 1000 degrees C stable HfLaON p-MOSFET with Ir3Si gate. Low leakage current of 1.8 x 10(-5) A/cm(2) at 1 V above flat-band voltage, good effective work function of 5.08 eV, and high mobility of 84 cm(2)/V center dot s are simultaneously obtained at 1.6 nm equivalent oxide thickness. This gate-first p-MOSFET process with self-aligned ion implant and 1000 degrees C rapid thermal annealing is fully compatible to current very large scale integration fabrication lines.
Low V-t gate-first Al/TaN/[Ir3Si-HfSi2-x]/HfLaON CMOS using simple laser annealing/reflection
(2008)
Liao, C. C.
;
Chin, Albert
;
Su, N. C.
;
Li, M. -F.
;
Wang, S. J.
We report low V-t Al/TaN/[Ir3Si-HfSi2-x]/HfLaON CMOS using simple laser annealing/reflection with self-aligned and gate-first process compatible with current VLSI. At 1.05 nm EOT, good phi(ro-eff) of 5.04 and 4.24 eV, low V-t of -0.16 and 0.13 V, high mobility of 85 and 209 cm(2)/Vs, and small 85 degrees C BTI <= 40 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.
Low V-t gate-first Al/TaN/[Ir3Si-HfSi2-x]/HfLaON CMOS using simple laser annealing/reflection
(2008-01-01)
Liao, C. C.
;
Chin, Albert
;
Su, N. C.
;
Li, M. -F.
;
Wang, S. J.
We report low V-t Al/TaN/[Ir3Si-HfSi2-x]/HfLaON CMOS using simple laser annealing/reflection with self-aligned and gate-first process compatible with current VLSI. At 1.05 nm EOT, good phi(m-eff) of 5.04 and 4.24 eV, low V-t of -0.16 and 0.13 V, high mobility of 85 and 209 cm(2)/Vs, and small 85 degrees C BTI <= 40 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.