Browsing by Author "Li, Walter Yuan-Hwa"

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Early Load: Hiding Load Latency in Deep Pipeline Processor
(2008)
Chang, Shun-Chieh
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Li, Walter Yuan-Hwa
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Kuo, Yuan-Jung
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Chung, Chung-Ping
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資訊工程學系
Load instructions usually have long execution latency in a deep processor pipeline, and have significant impact on overall performance. Therefore, how to hide the load latency becomes a serious problem in processor design. The latency of memory load can be separated into two parts: cache-miss latency and load-to-use latency. Previous work which tried to hide the load latency in a deep processor pipeline has some limitations. In this paper, we propose a hardware-based method, called early load, to hide the load-to-use latency with little hardware overhead. Early load scheme allows load instructions to load data from the cache system before it enters the execution stage. In the meantime, a detection method makes sure the correctness of the early operation before the load instruction enters the execution stage. Our experimental results showed that our approach can achieve 11.64% performance improvement in Dhrystone benchmark and 4.97% in average for MiBench benchmark suite.
Mechanism for Return Stack and Branch History Corrections under Misprediction in Deep Pipeline Design
(2008)
Chiu, Guan-Ying
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Yang, Hui-Chin
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Li, Walter Yuan-Hwa
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Chung, Chung-Ping
;
資訊工程學系
Return stack may be popped due to branch misprediction, corrupting its contents. Meanwhile, erroneous branch history is also recorded for upcoming branch predictions. These errors are more likely in deep pipelines, and their handling affects performance seriously. We study these issues, and propose solutions with two virtues: low hardware overhead, and high branch prediction accuracy comparable with that of a shallow pipeline design. To deal with return stack corruption, any push and pop after any mispredicted branch should be counted and recorded. These simple rules get overly complicated when multiple unresolved branches exist, and anyone may be erroneous, as is common in deeper pipelines. Next, to deal with branch history contamination, extra history bits, plus a branch confirmation pointer are needed. The experiment result shows that our design is effective, about 4%similar to 9% performance improvement in MiBench.