Browsing by Author "Li, Wenwu"

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Ambipolar MoTe2 Transistors and Their Applications in Logic Circuits
(2014-05-28)
Lin, Yen-Fu
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Xu, Yong
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Wang, Sheng-Tsung
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Li, Song-Lin
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Yamamoto, Mahito
We report ambipolar charge transport in a-molybdenum ditelluride (MoTe2) flakes, whereby the temperature dependence of the electrical characteristics was systematically analyzed. The ambipolarity of the charge transport originated from the formation of Schottky barriers at the metal/MoTe2 contacts. The Schottky barrier heights as well as the current on/off ratio could be modified by modulating the electrostatic fields of the back-gate voltage (V-bg) and drain-source voltage (V-ds). Using these ambipolar MoTe2 transistors we fabricated complementary inverters and amplifiers, demonstrating their feasibility for future digital and analog circuit applications.
Atomically thin van der Waals tunnel field-effect transistors and its potential for applications
(2019-03-08)
Yang, Shih-Hsien
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Yao, You-Teng
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Xu, Yong
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Lin, Che-Yi
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Chang, Yuan-Ming
Power dissipation is a crucial problem as the packing density of transistors increases in modern integrated circuits. Tunnel field-effect transistors (TFETs), which have high energy filtering provided by band-to-band tunneling (BTBT), have been proposed as an alternative electronics architecture to decrease the energy loss in bias operation and to achieve steep switching at room temperature. Very recently, the BTBT behavior has been demonstrated in van der Waals heterostructures by using unintentionally doped semiconductors. The reason of the BTBT formation is attributed to a significant band bending near the heterointerface, resulting in carrier accumulations. In this work, to investigate charge transport in type-III transistors, we adopted the same band-bending concept to fabricate van der Waals BP/MoS2 heterostructures. Through analyzing the temperature dependence of their electrical properties, we carefully ruled out the contribution of metal-semiconductor contact resistances and improved our understanding of carrier injection in 2D type-III transistors. The BP/MoS2 heterostructures showed both negative differential resistance and 1/f(2) current fluctuations, strongly demonstrating the BTBT operation. Finally, we also designed a TFET based on this heterostructure with an ionic liquid gate, and this TFET demonstrated an subthreshold slope can successfully surmount the thermal limit of 60 mV/decade. This work improves our understanding of charge transport in such layered heterostructures and helps to improve the energy efficiency of next-generation nanoscale electronics.
High Mobilities in Layered InSe Transistors with Indium-Encapsulation-Induced Surface Charge Doping
(2018-11-02)
Li, Mengjiao
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Lin, Che-Yi
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Yang, Shih-Hsien
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Chang, Yuan-Ming
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Chang, Jen-Kuei
Tunability and stability in the electrical properties of 2D semiconductors pave the way for their practical applications in logic devices. A robust layered indium selenide (InSe) field-effect transistor (FET) with superior controlled stability is demonstrated by depositing an indium (In) doping layer. The optimized InSe FETs deliver an unprecedented high electron mobility up to 3700 cm(2) V-1 s(-1) at room temperature, which can be retained with 60% after 1 month. Further insight into the evolution of the position of the Fermi level and the microscopic device structure with different In thicknesses demonstrates an enhanced electron-doping behavior at the In/InSe interface. Furthermore, the contact resistance is also improved through the In insertion between InSe and Au electrodes, which coincides with the analysis of the low-frequency noise. The carrier fluctuation is attributed to the dominance of the phonon scattering events, which agrees with the observation of the temperature-dependent mobility. Finally, the flexible functionalities of the logic-circuit applications, for instance, inverter and not-and (NAND)/not-or (NOR) gates, are determined with these surface-doping InSe FETs, which establish a paradigm for 2D-based materials to overcome the bottleneck in the development of electronic devices.
Low-Voltage Operational, Low-Power Consuming, and High Sensitive Tactile Switch Based on 2D Layered InSe Tribotronics
(2019-05-09)
Li, Mengjiao
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Yang, Feng-Shou
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Hsiao, Yung-Chi
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Lin, Che-Yi
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Wu, Hsing-Mei
Electronics based on layered indium selenide (InSe) channels exhibit promising carrier mobility and switching characteristics. Here, an InSe tribotronic transistor (denoted as w/In InSe T-FET) obtained through the vertical combination of an In-doped InSe transistor and triboelectric nanogenerator is demonstrated. The w/In InSe T-FET can be operated by adjusting the distance between two triboelectrification layers, which generates a negative electrostatic potential that serves as a gate voltage to tune the charge carrier transport behavior of the InSe channel. Benefiting from the surface charging doping of the In layer, the w/In InSe T-FET exhibits high reliability and sensitivity with a large on/off current modulation of 10(6) under a low drain-source voltage of 0.1 V and external frictional force. To demonstrate its function as a power-saving tactile sensor, the w/In InSe T-FET is used to sense INSE in Morse code and power on a light-emitting diode. This work reveals the promise of 2D material-based tribotronics for use in nanosensors with low power consumption as well as in intelligent systems.
Oxidation-boosted charge trapping in ultra-sensitive van der Waals materials for artificial synaptic features
(2020-06-12)
Yang, Feng-Shou
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Li, Mengjiao
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Lee, Mu-Pai
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Ho, I-Ying
;
Chen, Jiann-Yeu
Exploitation of the oxidation behaviour in an environmentally sensitive semiconductor is significant to modulate its electronic properties and develop unique applications. Here, we demonstrate a native oxidation-inspired InSe field-effect transistor as an artificial synapse in device level that benefits from the boosted charge trapping under ambient conditions. A thin InOx layer is confirmed under the InSe channel, which can serve as an effective charge trapping layer for information storage. The dynamic characteristic measurement is further performed to reveal the corresponding uniform charge trapping and releasing process, which coincides with its surface-effect-governed carrier fluctuations. As a result, the oxide-decorated InSe device exhibits nonvolatile memory characteristics with flexible programming/erasing operations. Furthermore, an InSe-based artificial synapse is implemented to emulate the essential synaptic functions. The pattern recognition capability of the designed artificial neural network is believed to provide an excellent paradigm for ultra-sensitive van der Waals materials to develop electric-modulated neuromorphic computation architectures. Developing efficient memory and artificial synaptic systems based on environmentally sensitive van der Waals materials remains a challenge. Here, the authors present a native oxidation-inspired InSe field-effect transistor that benefits from a boosted charge trapping behavior under ambient conditions.
The impact of electrical contacts and contact-induced ultralow noise amplitudes in layered transistors
(2016-12)
Hsu, Chih-Kai
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Lin, Chi-Yi
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Li, Wenwu
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Sun, Huabin
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Xu, Yong
Electrical contacts made of conducting channels with external circuitry significantly impact electronic performances, in particular for two-dimensional semiconductors. This work presents a systematic study of back-to-back Schottky contacts to a layered compound of semiconducting flakes through static and dynamic electrical measurements and the first demonstration of Schottky barrier-dominated, p-type PbSnS2 field-effect transistors. In the static analysis, the Schottky barrier height of the layered transistors can be modulated by applied electrostatic fields, while the contact-dominated fluctuations render to the 1/f electric noise and induce a normalized noise amplitude in the order of 10(-9)-10(-8). Such an ultralow-noise amplitude, which is never observed in other layered semiconducting transistors, is ascribed to the existence of Schottky barriers. Our experimental results provide a nuanced perspective for advancing the understanding of performance limit with increasing numbers of layers for electronic development.