Browsing by Author "Li, Yao"

Now showing 1 - 7 of 7

A 446.6K-Gates 0.55-1.2V H.265/HEVC Decoder for Next Generation Video Applications
(2013)
Tsai, Chang-Hung
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Wang, Hsiuan-Ting
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Liu, Chia-Lin
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Li, Yao
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Lee, Chen-Yi
An architecture of H. 265/HEVC video decoder for next generation video applications is presented. By exploiting near-lossless data compression and Sharing Above Line Buffer (SALB) schemes, both memory bandwidth and on-chip storage can be reduced. Moreover, cross-stage scheduling is applied to the 4-stage decoding pipeline to minimize idle computations. Fabricated in 90nm 1P9M CMOS process, the test chip of the proposed H. 265/HEVC video decoder occupies an area of 1.60x1.98mm(2) to achieve 1080p@30fps and 720p@30fps real-time decoding with power consumption of 36.90 and 9.57mW.
A Memory-Efficient Architecture for Intra Predictor and De-Blocking Filter in Video Coding System
(2012)
Liu, Chia-Lin
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Tsai, Chang-Hung
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Wang, Hsiuan-Ting
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Li, Yao
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Lee, Chen-Yi
In the hardware architecture of the H. 264/AVC video coding systems, the storage size of the intra predictor and deblocking filter occupies a great portion of the internal memory size in the video coding. However, the higher resolution video costs huge internal memory size to store pixels to predict block data and eliminate the blocking effect, especially for the next-generation video applications which target resolution is Ultra-HD (8Kx4K). In this article, a memory-efficient architecture for intra predictor and de-blocking filter has been proposed which can roughly reduce up to 19% internal memory usage to efficiently reduce the decoder size and power consumption, and the sequential-interleaving memory architecture has also been adopted in the proposed architecture to solve the memory access conflict during video decoding. A test module is designed for the proposal and operates at 200 MHz for real-time processing with 85.1 K gates and 8.4 KB SRAM in 90nm CMOS technology.
A Novel Embedded Bandwidth-Aware Frame Compressor for Mobile Video Applications
(2008)
Wu, Yu-De
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Li, Yao
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Lee, Chen-Yi
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
To reduce the bandwidth requirement and the size of frame memory for video decoding, embedding a compressor/decompressor on the chip is a well-known solution. Video compression has been developed for a long time and numbers of algorithm have been proposed. Those algorithms show us that enhancing the complexity can reach better performance. However, algorithm with higher complexity is more difficult to be embedded in a video decoder system. Longer coding cycles and lager gate counts may become a heavy load of the original system. In this paper, a new embedded compressor/decompressor algorithm is proposed for H.264 video compression. It is a lossy compression formed by two dimensions discrete cosine transform and modified bit plane zonal coding. The proposed algorithm compresses the 4x4 size block into a 64 bits segment, and decompresses A frame into 4x4 blocks. The compression ratio is fixed at two. With pipelined architecture, it takes 72 cycles and 34 cycles per MB for encoding and decoding respectively. As a result, our proposal becomes flexible to be embedded with any video coding system to save power consumption while maintaining acceptable video quality.
A Predefined Bit-Plane Comparison Coding for Mobile Video Applications
(2011-07-01)
Lin, Chien-Chen
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Li, Yao
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Lee, Chen-Yi
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
For mobile video applications, the required storage and bandwidth of frame memory play crucial roles. Reducing the accesses and the size of frame memory can decrease area and cost, as well as power consumption. Current video-coding standards can reach high compression efficiency but demand large volumes of computations and storage requirements. Hence, it is hard for these coding standards to be embedded into an H. 264 decoder. In this brief, a novel embedded lossy compression scheme is proposed. With a compression ratio at 2, it compresses a 4 x 2 size block into 32 bit with peak-signal-to-noise-ratio loss of 1.27 similar to 3.94 dB compared with H.264. A pipelined architecture is also proposed to realize both the compressor and the decompressor in 2 cycles and 1 cycle, respectively. This cost-effective solution requires a gate count of 4.9 k and power consumption of 244 mu W in a 90-nm standard complementary metal-oxide-semiconductor process, making it very suitable for mobile video applications.
An Area-efficient High-accuracy Prediction-based CABAC Decoder Architecture for H.264/AVC
(2011)
Kuo, Ming-Yu
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Li, Yao
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Lee, Chen-Yi
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper proposed a high-accuracy prediction scheme and area-efficient CABAC decoder architecture for H. 264 video decoder. To alleviate hardware cost and keep high throughput, we propose the prediction process and optimize the memory system. In particular, simulation results show that the proposed prediction-based CABAC decoder module achieves over 90% hit rate and requires only 16K logic gates with 3,360 bits SRAM by UMC 90 nm technology. The proposed architecture operates on 150 MHz frequency (Max. 249 MHz) for realizing 1080HD video playback at 30 fps, which can achieve Level 5.0 MP in tiny gate count.
Design of A Memory-Based VLC Decoder for Portable Video Applications
(2008)
Lee, Wei-Chin
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Li, Yao
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Lee, Chen-Yi
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, a VLC decoder supporting to decode coefficient data in blocks of MPEG-2 and CAVLC in H.264 is presented. To achieve programmability of the VLC decoder, a memory-based architecture with improved memory efficiency is proposed. Group-based look-up table (LUT) algorithm is extended to multi-table merging (MTM) which extracts redundancy of groups further. With multi-table merging algorithm, all coding tables are integrated into memory more efficiently. While the memory access may lead to much power consumption, a low-power scheme is proposed to reduce memory access. The distributed cache is adopted to save power and improve the decoding throughput as well. Simulation results show that the cache with replacement method can reduce about 60% similar to 95% memory accesses.
Design of An Intra Predictor with Data Reuse for High-Profile H.264 Applications
(2009)
Lai, Yu-Fan
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Liu, Tsu-Ming
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Li, Yao
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Lee, Chen-Yi
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電子工程學系及電子研究所
This paper presents a high-profile intra predictior for H.264 video decoder. To alleviate the starved bandwidth of intra compensation in high-definition video, we reuse the neighboring pixels and optimize the buffer size and access latency. In particular, a dedicated pixel buffer reuses neighboring pixel for realizing MB-adaptive frame-field (MBAFF) decoding in intra compensation. Moreover, a base-mode predictor is explored to optimize the area efficiency for reference sample filtering process (RSFP) in intra 8x8 modes. Simulation results show that the proposed data-reused intra prediction module requires 14K logic gates and 688 bits SRAM, and operates on 100MHz frequency for realizing 1080HD video playback at 30fps.