Browsing by Author "Li, Yi"

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Delivery of paclitaxel and cetuximab by nanodiamond enhances mitotic catastrophe and tumor inhibition in colorectal cancer
(2016-04-01)
Lin, Yu-Wei
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Liao, Wei-Siang
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Lin, Johnson
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Liu, Kuang-Kai
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Cheng, Hsiao-Chun
Delivery of paclitaxel and cetuximab by nanodiamond enhances mitotic catastrophe and tumor inhibition in colorectal cancer
(2016-04-01)
Lin, Yu-Wei
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Liao, Wei-Siang
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Lin, Johnson
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Liu, Kuang-Kai
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Cheng, Hsiao-Chun
Efficient Implementation of Boolean and Full-Adder Functions With 1T1R RRAMs for Beyond Von Neumann In-Memory Computing
(2018-10-01)
Wang, Zhuo-Rui
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Li, Yi
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Su, Yu-Ting
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Zhou, Ya-Xiong
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Cheng, Long
In-memory computing architecture is an emerging revolutionary computing paradigm that can break the von Neumann bottleneck. Computing methodology and circuit codesign using the CMOS compatible 1T1R resistive random access memory (RRAM) integration structure is presented in this paper. Functionally complete Boolean logic and arithmetic functions are experimentally demonstrated. With a single 40-nm CMOS process 1T1R unit, each of the 16 binary logics can be realized in two logic steps with an additional readout step for cascading, which shows functional reconfiguration and low computational complexity. Up to 10(7) cycles of NAND and XOR logic operations are performed to validate the correctness and reliability. Moreover, several fundamental adder circuits are designed and experimentally demonstrated in 1T1R devices as the proof of concept of the 1T1R computing architecture. The adders proposed in this paper include a ripple-carry adder and its optimized design and a carry-select adder, which all show promising advantages in nonvolatility, computation speed, and circuit area. This paper reports the most complex yet efficient RRAM-based 8-bit addition function experimentally so far and lays a solid foundation for constructing the future in-memory computing architecture.
Functionally Complete Boolean Logic in 1T1R Resistive Random Access Memory
(2017-02)
Wang, Zhuo-Rui
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Su, Yu-Ting
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Li, Yi
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Zhou, Ya-Xiong
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Chu, Tian-Jian
Nonvolatile stateful logic through RRAM is a promising route to build in-memory computing architecture. In this letter, a logic methodology based on 1T1R structure has been proposed to implement functionally complete Boolean logics. Arbitrary logic functions could be realized in two steps: initialization and writing. An additional read step is required to read out the logic result, which is in situ stored in the nonvolatile resistive state of the memory. Cascade problem in building larger logic circuits is also discussed. Our 1T1R logic device and operation method could be beneficial for massive integration and practical application of RRAM-based logic.
High-Precision Symmetric Weight Update of Memristor by Gate Voltage Ramping Method for Convolutional Neural Network Accelerator
(2020-03-01)
Chen, Jia
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Pan, Wen-Qian
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Li, Yi
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Kuang, Rui
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He, Yu-Hui
Memristor emerges as the key enabler for neural network accelerator. Here, we demonstrate high-precision symmetric weight update in a one transistor one resistor (1T1R) structure Ti/HfO2/TiN memristor using a gate voltage ramping method, with over 120-level states and low variation (< 4%). Incorporating all experimental non-idealities, the proposed mixed hardware-software convolutional neural network demonstrates over 92.79% online learning accuracy (against software equivalent 98.45%) for MNIST recognition task. The network also shows robustness to input image noises, array yield, and retention issues.
In-Memory Digital Comparator Based on a Single Multivalued One-Transistor-One-Resistor Memristor
(2020-03-01)
Cheng, Long
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Zheng, Hao-Xuan
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Li, Yi
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Chang, Ting-Chang
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Sze, Simon M.
In-memory computing based on multivalued memristive device opens the vision of building computing system with less resource and high performance. In this article, we achieved three distinguishable resistance states in mature one-transistor-one-resistor (1T1R) memristor. Furthermore, based on a single multivalued 1T1R device, for the first time, we successfully demonstrated an area-efficient in-memory digital comparator, which will cost five logic gates in complementary metal oxide semiconductor (CMOS) approach. The method is also easily expanded to multibit. Our work could be a representative of using multivalued nonvolatile memory device in digital information processing with improved performance.
LiSiOX-Based Analog Memristive Synapse for Neuromorphic Computing
(2019-04-01)
Chen, Jia
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Lin, Chih-Yang
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Li, Yi
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Qin, Chao
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Lu, Ke
The progress in the neuromorphic computing hinges on the development of nanoscale analog artificial synapses. Here, we report a LiSiOX (LSO)-based memristive synapse with 100-level conductance states under identical pulses, representing synaptic potentiation and depression behaviors. The superior analog behaviors originate from the dynamic evolution of an electro-thermal modulation region with the motion of lithium and oxygen ions. A three-layer perceptron was constructed in simulation with LSO synapses, and a 91.97% recognition accuracy was achieved for handwritten digits. Moreover, the influences of several critical parameters, including device variability and weight precision, on the accuracy have been investigated. This letter provides guidelines for the optimization of synaptic device in robust memristive neural network.
Neutrino physics with JUNO
(2016-03)
An, Fengpeng
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An, Guangpeng
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An, Qi
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Antonelli, Vito
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Baussan, Eric
The Jiangmen Underground Neutrino Observatory (JUNO), a 20 kton multipurpose underground liquid scintillator detector, was proposed with the determination of the neutrino mass hierarchy (MH) as a primary physics goal. The excellent energy resolution and the large fiducial volume anticipated for the JUNO detector offer exciting opportunities for addressing many important topics in neutrino and astro-particle physics. In this document, we present the physics motivations and the anticipated performance of the JUNO detector for various proposed measurements. Following an introduction summarizing the current status and open issues in neutrino physics, we discuss how the detection of antineutrinos generated by a cluster of nuclear power plants allows the determination of the neutrino MH at a 3-4 sigma significance with six years of running of JUNO. The measurement of antineutrino spectrum with excellent energy resolution will also lead to the precise determination of the neutrino oscillation parameters sin(2) theta(12), Delta m(21)(2), and vertical bar Delta m(ee)(2)vertical bar to an accuracy of better than 1%, which will play a crucial role in the future unitarity test of the MNSP matrix. The JUNO detector is capable of observing not only antineutrinos from the power plants, but also neutrinos/antineutrinos from terrestrial and extra-terrestrial sources, including supernova burst neutrinos, diffuse supernova neutrino background, geoneutrinos, atmospheric neutrinos, and solar neutrinos. As a result of JUNO\'s large size, excellent energy resolution, and vertex reconstruction capability, interesting new data on these topics can be collected. For example, a neutrino burst from a typical core-collapse supernova at a distance of 10 kpc would lead to similar to 5000 inverse-beta-decay events and similar to 2000 all-flavor neutrino-proton ES events in JUNO, which are of crucial importance for understanding the mechanism of supernova explosion and for exploring novel phenomena such as collective neutrino oscillations. Detection of neutrinos from all past core-collapse supernova explosions in the visible universe with JUNO would further provide valuable information on the cosmic star-formation rate and the average core-collapse neutrino energy spectrum. Antineutrinos originating from the radioactive decay of uranium and thorium in the Earth can be detected in JUNO with a rate of similar to 400 events per year, significantly improving the statistics of existing geoneutrino event samples. Atmospheric neutrino events collected in JUNO can provide independent inputs for determining the MH and the octant of the theta(23) mixing angle. Detection of the Be-7 and B-8 solar neutrino events at JUNO would shed new light on the solar metallicity problem and examine the transition region between the vacuum and matter dominated neutrino oscillations. Regarding light sterile neutrino topics, sterile neutrinos with 10-(5) eV(2) < Delta m(41)(2) < 10(-2) and a sufficiently large mixing angle theta(14) could be identified through a precise measurement of the reactor antineutrino energy spectrum. Meanwhile, JUNO can also provide us excellent opportunities to test the eV-scale sterile neutrino hypothesis, using either the radioactive neutrino sources or a cyclotron-produced neutrino beam. The JUNO detector is also sensitive to several other beyondthe-standard-model physics. Examples include the search for proton decay via the p -> K++ <(v)over bar> decay channel, search for neutrinos resulting from dark-matter annihilation in the Sun, search for violation of Lorentz invariance via the sidereal modulation of the reactor neutrino event rate, and search for the effects of non-standard interactions. The proposed construction of the JUNO detector will provide a unique facility to address many outstanding crucial questions in particle and astrophysics in a timely and cost-effective fashion. It holds the great potential for further advancing our quest to understanding the fundamental properties of neutrinos, one of the building blocks of our Universe.
Nonvolatile reconfigurable sequential logic in a HfO2 resistive random access memory array
(2017-05-28)
Zhou, Ya-Xiong
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Li, Yi
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Su, Yu-Ting
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Wang, Zhuo-Rui
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Shih, Ling-Yi
Resistive random access memory (RRAM) based reconfigurable logic provides a temporal programmable dimension to realize Boolean logic functions and is regarded as a promising route to build non-von Neumann computing architecture. In this work, a reconfigurable operation method is proposed to perform nonvolatile sequential logic in a HfO2-based RRAM array. Eight kinds of Boolean logic functions can be implemented within the same hardware fabrics. During the logic computing processes, the RRAM devices in an array are flexibly configured in a bipolar or complementary structure. The validity was demonstrated by experimentally implemented NAND and XOR logic functions and a theoretically designed 1-bit full adder. With the trade-off between temporal and spatial computing complexity, our method makes better use of limited computing resources, thus provides an attractive scheme for the construction of logic-in-memory systems.
Reconfigurable Boolean Logic in Memristive Crossbar: The Principle and Implementation
(2019-02-01)
Hu, Si-Yu
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Li, Yi
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Cheng, Long
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Wang, Zhuo-Rui
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Chang, Ting-Chang
In-memory computing based on memristive logic is considered as a prospective non von Neumann computing paradigm. In this letter, we systematically analyze the four-variable logic method and map it into the operation of two anti-serial complementary memristors in the crossbar array architecture. Arbitrary Boolean logic can be implemented within three cycles with the experimental evidence of reconfigurable NAND, NOR, and XOR logic using Pt/HfO2/TiN devices. Taking advantage of the functional flexibility, a parallel 1-bit full adder that can be realized in 8 cycles within a 4 x 3 array has been designed and verified in simulation.