Browsing by Author "Li, Yiming"

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2005 international symposium of computational electronics: Physical modeling, mathematical theory, and numerical algorithm
(2005)
Li, Yiming
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電信工程研究所
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Institute of Communications Engineering
2008 International Symposium on Computational Management and Social Science
(2009)
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
2008 International Workshop on Scientific Computing in Electronics Engineering (WSCEE 2008) Preface
(2010-04-01)
Li, Yiming
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Dyshlovenko, Pavel
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Ezaki, Tatsuya
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Fjeldly, Tor A.
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Kosina, Hans
32-nm Multigate Si-nTFET With Microwave-Annealed Abrupt Junction
(2016-05)
Hou, Fu-Ju
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Sung, Po-Jung
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Hsueh, Fu-Kuo
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Wu, Chien-Ting
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Lee, Yao-Jen
Microwave annealing (MWA) activates dopants through solid-phase epitaxial regrowth with low thermal budget. Optimizing the microwave power during MWA is capable of realizing low defect density at the junction, suppressing the dopant diffusion, and mitigating the straggle effect of ion implantation. These favorable features of MWA facilitate the formation of extremely abrupt junction profiles in tunnel FETs (TFETs). In conjunction with the improved gate-to-channel controllability of the multiple-gate (MG) structure, we demonstrate high-performance lateral n-type Si-TFETs using a CMOS-compatible process flow with excellent band-to-band tunneling efficiency and device scalability. The 32-nm MG Si-TFET shows promising characteristics, including a high ON-state current of 41.3 mu A/mu m, a large current ON/OFF ratio of > 5 x 10(7), and minimal short-channel effect using V-G = 2 V and V-D = 1 V.
3D 65nm CMOS with 320 degrees C Microwave Dopant Activation
(2009)
Lee, Yao-Jen
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Lu, Yu-Lun
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Hsueh, Fu-Kuo
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Huang, Kuo-Chin
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Wan, Chia-Chen
For the first time, CMOS TFTs of 65nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is. demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF2 for p-MOS TFTs and P-31 for n-MOS TFTs at a low temperature of 320 degrees C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.
3D Device Simulation of Work Function and Interface Trap Fluctuations on High-kappa/Metal Gate Devices
(2010)
Cheng, Hui-Wen
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Li, Fu-Hai
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Han, Ming-Hung
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Yiu, Chun-Yen
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Yu, Chia-Hui
This work, for the first time, examines the work function fluctuation (WKF) and interface trap fluctuation (ITF) using experimentally calibrated 3D device simulation on high-kappa / metal gate technology. The random WKs result in 36.7 mV threshold voltage fluctuation (sigma V(th)) for 16 nm N-MOSFETs with TiN gate, which is rather different from the result of averaged WKF (AWKF) method [1] due to localized random WK effect. The ITF affects the subthreshold region (the normalized sigma I(D) > 48%) and is suppressed for devices under strong inversion. Estimation of statistical covariance confirms the dependence of IT on the metal gate's WK; thus, the impacts of WKF and ITF on device and circuit variability should be considered together properly. Such variability induced static noise margin fluctuation of SRAM exceeds the influence of random dopants and cannot be ignored.
50% Efficiency Intermediate Band Solar Cell Design Using Highly Periodical Silicon Nanodisk Array
(2012)
Hu, Weiguo
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Igarashi, Makoto
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Lee, Ming-Yi
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Li, Yiming
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Samukawa, Seiji
A high-quality Si nanodisk superlattice is fabricated by our top-down process. For the first time, a 3D finite element method (FEM) is developed to calculate energy band structure, optical and electrical properties, as well as the intermediate band solar cell (IBSC) operation for the realistic structure. Both the experiments and simulations reveal that miniband formation enhances the optical and electrical collections. Consequently, detailed electronic structure and conversion efficiency are examined to guide optimal design of minibands. A theoretically predicted maximal efficiency of the explored Si nanodisk superlattice is 50.3%, which is promising, compared with well-known complicated Si tandem solar cells.
A compact model for electrostatic discharge protection nanoelectronics simulation
(2005)
Chou, Hung-Mu
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Yu, Shao-Ming
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Lee, Jam-Wem
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Li, Yiming
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電信工程研究所
In nanoelectronics, snapback phenomena play an important role in electrostatic discharge (ESD) protection devices, in particular for gigascale, very large scale integration (VLSI) circuit design. In this paper we present a new ESD equivalent circuit model for deep submicrion and nanoscale semiconductor device simulation. By considering the geometry effect in the formulation of snapback characteristics, our model can be directly incorporated into electronic circuit simulation for the whole chip ESD protection circuit design. With the developed ESD model, we can investigate robust enhancement problems and perform a SPICE based whole chip ESD protection circuit design in nanoelectronics.
A comparative study of foreign direct investment flow using diffusion models
(2007)
Li, Yiming
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Chiang, Yi-Hui
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Yu, Shao-Ming
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Chiang, Su-Yun
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Hung, C. -H.
In this work, we apply an improvement dynamic model of the foreign direct investment (FDI) flow to analyze the evolution of FDI flow. In comparison with the fundamental growth model of FDI, the simulation result is further accurate if the asymmetric growth pattern and heterogeneity of the potential adopters are considered. According to the result, the internal influence dominates the growth of FDI flow from Taiwan to China during 2001-2006, taking the electronics industry for example.
A coupled-simulation-and-optimization approach to nanodevice fabrication with minimization of electrical characteristics fluctuation
(2007-11-01)
Li, Yiming
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Yu, Shao-Ming
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資訊工程學系
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電信工程研究所
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Department of Computer Science
In this paper, a simulation-based optimization methodology for nanoscale complementary metal-oxide-semiconductor (CMOS) device fabrication is advanced. Fluctuation of electrical characteristics is simultaneously considered and minimized in the optimization procedure. Integration of device and process simulation is implemented to evaluate device performances, where the hybrid intelligent approach enables us to extract optimal recipes which are subject to targeted device specification. Production of CMOS devices now enters the technology node of 65 nm; therefore, random-dopant-induced characteristic fluctuation should be minimized when a set of fabrication parameters is suggested. Verification of the optimization methodology is tested and performed for the 65-nm CMOS device. Compared with realistic fabricated and measured data, this approach can achieve the device characteristics; e.g., for the explored 65-nm n-type MOS field effect transistor, the on-state current > 0.35 mA/mu m, the off-state current < 1.5e - 11 A/mu m, and the threshold voltage = 0.43 V. Meanwhile, it reduces the threshold voltage fluctuation (sigma(vth) similar to 0.017 V). This approach provides an alternative to accelerate the tuning of process parameters and benefits manufacturing of nanoscale CMOS devices.
A distributed simulation-based computational intelligence algorithm for nanoscale semiconductor device inverse problem
(2006)
Li, Yiming
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Chen, Cheng-Kai
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電信工程研究所
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Institute of Communications Engineering
In this paper, a distributed simulation-based computational intelligence algorithm for inverse problem of nanoscale semiconductor device is presented. This approach features a simulation-based optimization strategy, and mainly integrates the semiconductor process simulation, semiconductor device simulation, evolutionary strategy, and empirical knowledge on a distributed computing environment. For a set of given target current-voltage (I-V) curves of metal-oxide-semi conductor field effect transistors (MOSFETs) devices, the developed prototype executes evolutionary tasks to solve an inverse doping profile problem, and therefore optimize fabrication recipes. In the evolutionary loop, the established management server allocates the jobs of process simulation and device simulation on a PC-based Linux cluster with message passing interface (MPI) libraries. Good benchmark results including the speed-up, the load balancing, and the parallel efficiency are presented. Computed results, compared with the realistic measured data of 65 nm n-type MOSFET, show the accuracy and robustness of the method.
A Dynamic Competition Analysis on the Personal Computer Shipments in Taiwan Using Lotka-Volterra Model
(2008)
Chiang, Su-Yun
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Wong, Gwo-Gauang
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Li, Yiming
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Yu, Hsiao-Cheng
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科技管理研究所
In this work, we explore the innovative growth of personal computer (PC) shipments in Taiwan. We estimate the marketing diffusion with the consideration of the competition of desktop (DT) and notebook (NB). Mathematically, using the Lotka-Volterra model, we analyze the dynamic competitive relationship between the shipments of DT and NB. All the parameters in the Lotka-Volterra model are calibrated with the realistic shipment data, and the predicted trends to 2010 are thus drawn. Our results clarify a pure competition between DT and NB in PC market. The competitive relationship of dynamic PC shipments in Taiwan is thus examined, including consideration of the interaction between two species to explain the actual diffusion phenomenon in the competitive market. Comparison between well-known growth model, Bass model, and competitive Lotka-Volterra Model is also drawn. In addition, it is shown that the competition between DT and NB would reach an equilibrium point which is stable over time and we further analyze how the deviation returns to the stable equilibrium.
A Dynamic Competition Simulation for Worldwide Big-size TV Market Using Lotka-Volterra Model
(2009)
Chen, Wu-Tung Terry
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Li, Yiming
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Hung, Chih-Young
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科技管理研究所
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Institute of Management of Technology
Technological innovation is characterized by the substitution of new technologies for full-fledged ones in the development of new products, processes and techniques. Global TV market is seeing a price down-spiral for FPD(Flat Panel Display) -TVs, replacement of CRT by LCD, and consumer's defection to larger screen. The LCD-TV market started in Japan from 2003 and took off globally from 2005. LCD panel production is moving toward larger sizes. In the 35"-39" size market, the price/performance ratio of LCD-TV is better than that of PDP. The purpose of this paper is to estimate the demand function of worldwide big-size (35"-39") TVs including LCD and PDP with an explicit consideration of market competition. The demand function was estimated using Lotka-Volterra model, a famous competitive diffusion model. The results exhibit a kind of predator-prey relationship, in which the PDP market was hunted by LCD product. In addition, the coefficients of difference equations of Lotka-Volterra model in this analysis are also used to forecast the future market of the big-size LCD and PDP.
A floating gate design for electrostatic discharge protection circuits
(2007-02-01)
Chou, Hung-Mu
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Lee, Jam-Wen
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Li, Yiming
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電信工程研究所
;
友訊交大聯合研發中心
In this paper, a circuit design method for electrostatic discharge (ESD) protection is presented. It considers the gate floating state for ESD protection and negatively gate biased for leakage suppression under normal operations. The circuit is achieved by adding a switch device and a negatively biased circuit at the gate of ESD protection devices. Robustness and leakage of ESD protection circuit are improved. The circuit suits thin thickness of gate oxide of complementary metal oxide semiconductor (CMOS) devices due to an elimination of oxide damage. This approach benefits design of very large-scaled integration circuit and implementation of system-on-chip with sub-100 nm CMOS devices. (c) 2006 Elsevier B.V. All rights reserved.
A hybrid multiuser detection technique based on interference cancellation knowledge in MIMO communications
(2007)
Pan, Chien-Hung
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Lee, Ta-Sung
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Li, Yiming
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電信工程研究所
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Institute of Communications Engineering
In this paper, we propose a hybrid multiuser detection (MUD) technique, which is similar to the maximum likelihood detector (MLD) but with reduced complexity, for the application of multiple-input multiple-output (MIMO) communications. The proposed MUD technique avoids the exhaustive search required for the elimination of inter-antenna interference (IAI). Instead, the proposed method incorporates an efficient hybrid multiuser detection technique and consists of a two-stage procedure to achieve the performance of the ML detector with an acceptable level of computational complexity. The first stage performs interference cancellation by using the sorted QR decomposition (SQRD), and the second stage performs the genetic algorithm (GA). This two-stage procedure is thus called SQRD GA-MUD. The main advantage of the SQRD scheme is that it provides a "good initial setting knowledge" by eliminating IAI to improve the fitness of the population for GA. Simulation results obtained in this study demonstrate that SQRD GA-MUD achieves a gain of 6 dB to 15 dB compared to other well known detectors, with an acceptable number of iterations.
A novel AlGaN/GaN multiple aperture vertical high electron mobility transistor with silicon oxide current blocking layer
(2015-08-01)
Shrestha, Niraj Man
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Wang, Yuen Yee
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Li, Yiming
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Chang, Edward Yi
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材料科學與工程學系
In this work, a new AlGaN/GaN vertical high electron mobility transistor (HEMT) with silicon oxide (SiO2) current blocking layer (CBL) is designed and studied numerically for high-power devices. To overcome the excessive vertical leakage through CBL layer in conventional p-GaN CBL vertical HEMT, large band-gap material, SiO2 is, for the first time, introduced as a CBL material. The band-gap of SiO2 leads to a large barrier which can effectively suppress the vertical leakage even at high drain bias and enhance the breakdown voltage to 1270 V (154% enhancement compared with the conventional p-GaN CBL vertical HEMT). In addition, a device with four parallel apertures is proposed to reduce the aperture resistance, where the total aperture thickness is equal to the aperture thickness of the conventional one. Therefore, the drain current is increased. We not only focus on the vertical leakage control, but also, on the drain current boost (7% improvement). (c) 2014 Elsevier Ltd. All rights reserved.
A Novel Approach to Compact Model Parameter Extraction for Excimer Laser Annealed Complementary Thin Film Transistors
(2004-10-01)
Li, Yiming
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Yu, Shao-Ming
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資訊工程學系
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電信工程研究所
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友訊交大聯合研發中心
A unified physical-based model parameter extraction technique for excimer laser annealed lower temperature polycrystalline silicon (LTPS) complementary thin film transistors (TFTs) is for the first time proposed. For two well-known compact models of LTPS TFT, Rensselaer Polytechnic Institute (RPI) V1 and V2 models, our approach sequentially optimizes the model parameters in the regions of linear, subthreshold, saturation, and leakage. Compared with the measured results, the extracted I-D - V-G, I-D - V-D, transconductance, and output conductance are within 3% of accuracy. The agreement with the experimental data is excellent for the n- and p-type LTPS TFTs with different length and width. This extraction technique bridges the fabrication of LTPS TFTs and the design of complementary system on panel circuits.
A Novel Driving Method for High-Performance Amorphous Silicon Gate Driver Circuits in Flat Panel Display Industry
(2016-10)
Chiang, Chien-Hsueh
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Li, Yiming
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電信工程研究所
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Institute of Communications Engineering
In this study, we report a novel driving method to operate the amorphous silicon gate (ASG) driver circuits in flat panel display. The principal modification is to change the type of the clock signals to two low levels in the ASG circuit. The proposed ASG driver circuit has been implemented using a five-mask amorphous silicon process for thin-film transistors. The fall time of the output in the tested ASG circuit with the novel driving method is about 30% shorter than that with the conventional driving method. Moreover, the minimum operation high voltage keeps the same level of the ASG circuit with the new clock driving. Notably, the proposed driving method causes merely 5.5% increment of the power consumption, compared with the conventional one.
A Quantum Correction Model for Nanoscale Double-Gate MOS Devices Under Inversion Conditions
(2003-12-01)
Li, Yiming
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Tang, Ting-Wei
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Yu, Shao-Ming
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資訊工程學系
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友訊交大聯合研發中心
A quantum correction model for nanoscale double-gate MOSFETs under inversion conditions is proposed. Based on the solution of Schrodinger-Poisson equations, the developed quantum correction model is optimized with respect to (i) the left and right positions of the charge concentration peak, (ii) the maximum of the charge concentration, (iii) the total inversion charge sheet density, and (iv) the average inversion charge depth, respectively. This model can predict inversion layer electron density for various oxide thicknesses, silicon film thicknesses, and applied voltages. Compared to the Schrodinger-Poisson results, our model prediction is within 3.0% of accuracy. This quantum correction model has continuous derivatives and is therefore amenable to a device simulator.
A simulation-based evolutionary approach to LNA circuit design optimization
(2009-03-01)
Li, Yiming
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電信工程研究所
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Institute of Communications Engineering
In this paper, we propose a simulation-based evolutionary approach for designing low noise amplifier (LNA) integrated circuits (ICs). Based on a genetic algorithm (GA), the Levenberg-Marquardt (LM) method, and a circuit simulator, the simulation-based evolutionary approach is developed for design optimization of LNA circuits. For a given LNA circuit, the simulation-based evolutionary approach simultaneously optimizes the electrical specifications, such as S(11), S(12), S(21), S(22), K factor, the noise figure, and the input third-order intercept point in the process between simulation and optimization. First of all, the necessary parameters of the LNA circuit for circuit simulation are loaded. By solving a set of non-linear ordinary differential equations, the circuit simulator will then be performed for the circuit simulation and specification evaluation. Once the specification meets the aforementioned seven constraints, we output the optimized parameters. Otherwise, we activate the GA for the global optimization; in the meanwhile, the LM method searches the local optima according to the results of the GA. We then call circuit simulator to compute and evaluate newer results until the specification is matched. In numerical experiment, 10 parameters of the LNA circuit including device configuration and biasing condition are optimized with respect to the constraints. The design of LNA circuit is with 0.18 mu m metal-oxide-silicon filed effect transistors. Benchmark results also computationally confirm the robustness and efficiency of the proposed method. This simulation-based evolutionary approach, in general can be applied to optimal design of other analog and radio frequency circuits. We believe that this systematical approach will help IC design optimization, and benefit computer-aided design of wireless communication system-on-a-chip. (C) 2008 Elsevier Inc. All rights reserved.