Browsing by Author "Li, Yuan-Ping"

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A variable step-size sign algorithm for channel estimation
(2014-09-01)
Li, Yuan-Ping
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Lee, Ta-Sung
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Wu, Bing-Fei
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
This paper proposes a new variable step-size sign algorithm (VSSA) for unknown channel estimation or system identification, and applies this algorithm to an environment containing two-component Gaussian mixture observation noise. The step size is adjusted using the gradient-based weighted average of the sign algorithm. The proposed scheme exhibits a fast convergence rate and low misadjustment error, and provides robustness in environments with heavy-tailed impulsive interference. (C) 2014 Elsevier B.V. All rights reserved.
Design of an FMCW radar baseband signal processing system for automotive application
(2016-01-18)
Lin, Jau-Jr
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Li, Yuan-Ping
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Hsu, Wei-Chiang
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Lee, Ta-Sung
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電機資訊學士班
For a typical FMCW automotive radar system, a new design of baseband signal processing architecture and algorithms is proposed to overcome the ghost targets and overlapping problems in the multi-target detection scenario. To satisfy the short measurement time constraint without increasing the RF front-end loading, a three-segment waveform with different slopes is utilized. By introducing a new pairing mechanism and a spatial filter design algorithm, the proposed detection architecture not only provides high accuracy and reliability, but also requires low pairing time and computational loading. This proposed baseband signal processing architecture and algorithms balance the performance and complexity, and are suitable to be implemented in a real automotive radar system. Field measurement results demonstrate that the proposed automotive radar signal processing system can perform well in a realistic application scenario.
Modular design and implementation of field-programmable-gate-array-based Gaussian noise generator
(2016-05-03)
Li, Yuan-Ping
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Lee, Ta-Sung
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Hwang, Jeng-Kuang
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電機工程學系
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Department of Electrical and Computer Engineering
The modular design of a Gaussian noise generator (GNG) based on field-programmable gate array (FPGA) technology was studied. A new range reduction architecture was included in a series of elementary function evaluation modules and was integrated into the GNG system. The approximation and quantisation errors for the square root module with a first polynomial approximation were high; therefore, we used the central limit theorem (CLT) to improve the noise quality. This resulted in an output rate of one sample per clock cycle. We subsequently applied Newton\'s method for the square root module, thus eliminating the need for the use of the CLT because applying the CLT resulted in an output rate of two samples per clock cycle (>200 million samples per second). Two statistical tests confirmed that our GNG is of high quality. Furthermore, the range reduction, which is used to solve a limited interval of the function approximation algorithms of the System Generator platform using Xilinx FPGAs, appeared to have a higher numerical accuracy, was operated at >350MHz, and can be suitably applied for any function evaluation.