Browsing by Author "Li Shih-Wei"

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ELECTRICAL TEST STRUCTURE APPLYING 3D-ICS BONDING TECHNOLOGY FOR STACKING ERROR MEASUREMENT
(2013-03-14)
Chen Kuan-Neng
;
Li Shih-Wei
A 3D integrated circuit including a first wafer and a second wafer is provided. The first wafer includes a first conduction pattern. The second wafer includes a second conduction pattern which is electrically connected to the first conduction pattern. A displacement between the first wafer and the second wafer is determined by a resistance of the first conduction pattern and the second conduction pattern.
Electrical test structure applying 3D-ICS bonding technology for stacking error measurement
(2013-10-01)
Chen Kuan-Neng
;
Li Shih-Wei
A 3D integrated circuit including a first wafer and a second wafer is provided. The first wafer includes a first conduction pattern. The second wafer includes a second conduction pattern which is electrically connected to the first conduction pattern. A displacement between the first wafer and the second wafer is determined by a resistance of the first conduction pattern and the second conduction pattern.