Browsing by Author "Liang, M. S."

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HfSiON n-MOSFETs using low-work function HfSi chi gate
(2006-09-01)
Wu, C. H.
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Hung, B. F.
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Chin, Albert
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Wang, S. J.
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Yen, F. Y.
The authors have developed a novel high-temperature stable HfSix gate for high-kappa HfSiON gate dielectric. After a 1000 degrees C RTA, the HfSix/HfSiON devices showed an effective work function of 4.27 eV and a peak electron mobility of 216 cm(2)/V (.) s at 1.6-nm equivalent oxide thickness, with additional merit of a process compatible with current very large scale integration fabrication lines.
High temperature stable [Ir3Si-TaN]/HfLaON CMOS with large work-function difference
(2006)
Wu, C. H.
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Hung, B. F.
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Chin, Albert
;
Wang, S. J.
;
Chen, W. J.
We report novel 1000 degrees C-stable [Ir3Si-TaN]/HfLaON CMOS for the first time, where the self-aligned and gate-first process are full compatible to current VLSI. Good phi(m.eff) of 5.08 and 4.24 eV, low V, of -0.10 and 0.18 V, high mobility of 84 and 217 cm(2)/Vs at 1.6 nm EOT, and small 850 degrees C BTI < 20 mV (10 MV/cm for 1 hr) are measured.
High-temperature stable HfLaON p-MOSFETs with high-work-function Ir3Si gate
(2007-04-01)
Wu, C. H.
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Hung, B. F.
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Chin, Albert
;
Wang, S. J.
;
Wang, X. P.
We report a novel 1000 degrees C stable HfLaON p-MOSFET with Ir3Si gate. Low leakage current of 1.8 x 10(-5) A/cm(2) at 1 V above flat-band voltage, good effective work function of 5.08 eV, and high mobility of 84 cm(2)/V center dot s are simultaneously obtained at 1.6 nm equivalent oxide thickness. This gate-first p-MOSFET process with self-aligned ion implant and 1000 degrees C rapid thermal annealing is fully compatible to current very large scale integration fabrication lines.
Mechanical properties and fracture mechanism of porous SiOCH low-k dielectrics
(2011-07-01)
Chang, H. L.
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Kuo, C. T.
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Liang, M. S.
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材料科學與工程學系
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高階主管管理碩士學程
A series of low-k dielectric films with various mechanical properties were prepared for a 32-nm back-end-of-line technology node. Various precursors were used, and the porogen removal treatment was performed using the H(2) or E-beam-assisted method. This study presents a novel approach for determining the loss of materials during treatment. This approach includes determining yield strength, fracture toughness, bonding structure, and fracture mechanism of a series of low-k silica films. The results show that a low-k film formed using the precursor trimethylsilane has higher yield strength and fracture toughness than the low-k films formed using the precursor tetramethylsilane or octamethylcyclotetrasiloxane. The residual gas analysis was conducted to determine the loss of materials and predict the bonding structure: the results show that the E-beam treatment rearranges the structure more effectively than the H(2) treatment by using the H radial to decompose the methyl group. Finally, the fracture mechanism of these low-k films was determined by relating the crack patterns of the indents on these films to their indentation load-displacement curves. (C) 2011 Elsevier B.V. All rights reserved.
Oxygen vacancy estimation of high k metal gate using thermal dynamic model
(2010-07-26)
Chang, H. L.
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Liang, M. S.
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材料科學與工程學系
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Department of Materials Science and Engineering
Oxygen vacancies are electronic defects in materials. In a metal oxide system, the distribution of such vacancies is determined by the oxygen affinity. This study predicts the oxygen vacancy concentration in a high-k/metal gate system using a developed thermal dynamic model. A system with Ti:N=2 has a 200 mV lower flat band voltage than an N rich metal. The Gibbs free energy of formation of oxygen vacancies, similar to 0.5 eV, is derived from flab band voltage shifts and created neutral oxygen vacancy. The oxygen vacancy model based on estimating thermal dynamics is proposed. (C) 2010 American Institute of Physics. [doi:10.1063/1.3473772]
Relaxation-free strained SiGe with super anneal for 32nm high performance PMOS and beyond
(2006)
Yu, Ming H.
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Li, J. H.
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Lin, H. H.
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Chen, C. H.
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Ku, K. C.
The interaction of epitaxially strained SiGe and super annealing or millisecond anneal in high performance PFET fabrication was, for the first time, systematically investigated. When super annealing was applied, the quality of SiGe/Si interface, affected by subsequent ion implantation and post-SiGe thermal treatment, played an important role in SiGe strain relaxation incurring channel stress loss and defect injection to Si substrate resulting in high junction leakage. Defect injection mechanism was proposed to explain the defect formation in Si substrate. The new processing scheme, which preserved SiGe as relaxation-free and avoided defect injection, was developed and for 32nm technology. The device performance gain with 10% Id,sat increment resulting from fully strained SiGe was achieved.
The Dependence of the Performance of Strained NMOSFETs on Channel Width
(2009-11-01)
Yeh, Lingyen
;
Liao, Ming Han
;
Chen, Chun Heng
;
Wu, Jun
;
Lee, Joseph Ya-Min
The dependence of the performance of strained NMOSFETs on channel width was investigated. When the channel width was varied, the stress in the channel varied accordingly. This changed the electron effective mass and, consequently, the ON-state current I(on). By shrinking the channel width of a strained NMOSFET from 1 to 0.1 mu m and by keeping the channel length at 55 nm, the ON-state drain current per unit channel width was enhanced by 22%. The gate leakage current was also affected by the stress in the channel, which can be explained by the increase in hole barrier height at the Si/SiO(2) interface. Furthermore, when the film stress was increased by 1 GPa, the gate leakage current density J(g) of a strained NMOSFET with a channel width of 0.1 mu m and a length of 55 nm under a negative bias -3 V was reduced by 63%.