Browsing by Author "Liang, MS"

Now showing 1 - 20 of 54

A new bride damage characterization technique for evaluating hot carrier reliability of flash memory cell after P/E cycles
(1997)
Chung, SS
;
Yih, CM
;
Cheng, SM
;
Liang, MS
;
交大名義發表
A new technique for hot carrier reliability evaluations of flash memory cell after long-term program/erase cycles
(1999-09-01)
Chung, SS
;
Yih, CM
;
Cheng, SM
;
Liang, MS
;
電子工程學系及電子研究所
In this paper, we provide a methodology to evaluate the hot-carrier-induced reliability of hash memory cells after long-term program/erase cycles. First, the gated-diode measurement technique has been employed for determining the lateral distributions of interface state (N-it) and oxide trap charges (Q(ox)) under both channel-hot-electron (CHE) programming bias and source-side erase-bias stress conditions. A gate current model was then developed by including both the effects of N-it and Q(ox), Degradation of flash memory cell after P/E cycles due to the above oxide damage was studied by monitoring the gate current. For the cells during programming, the oxide damage near the drain will result in a programming time delay, and we found that the interface state generation iis the dominant mechanism. Furthermore, for the cells after long-term erase using source-side FN erase, the oxide trap charge will dominate the cell performance such as read-disturb. In order to reduce the read-disturb, source bias should be kept as low as possible since the larger the applied source erasing bias, the worse the device reliability becomes.
A physical model for hole direct tunneling current in P+ poly-gate PMOSFETs with ultrathin gate oxides
(2000-11-01)
Yang, KN
;
Huang, HT
;
Chang, MC
;
Chu, CM
;
Chen, YS
A model of the hole direct tunneling gate current accounting for heavy and light hole's subbands in the quantized inversion layer is built explicitly. This model comprises four key physical parameters: inversion layer charge density, hole impact frequency on SiO2/Si interface, WKB transmission probability, and reflection correction factor. With the effective hole mass m(oxh) = 0.5m(o) for parabolic dispersion relationship in the oxide, experimental reproduction without any parameter adjustment is consistently achieved in p(+) poly-gate pMOSFETs with 1.23, 1.85, and 2.16 nm gate oxide thicknesses. The proposed model can thereby serve as a promising characterization means of direct tunnel oxides. In particular, it is calculated that the secondary subbands and beyond, although occupying few holes, indeed contribute substantially to the direct tunneling conduction due to effective lo,vcr barrier heights, and are prevailing over the first subbands for reducing oxide field down below 1 MV/cm.
A physical model for the hysteresis phenomenon of the ultrathin ZrO2 film
(2002-10-01)
Wang, JC
;
Chiao, SH
;
Lee, CL
;
Lei, TF
;
Lin, YM
This work studies and presents an inner-interface trapping physical model for the ultra-thin (effective oxide thickness=15 Angstrom) zirconium oxide (ZrO2) film to explain its hysteresis phenomenon. The shift of the capacitance-voltage characteristics swept from accumulation to inversion and then swept back with light illumination is about 110 mV, which is larger than the shift without light illumination (similar to45 mV). The mobile ion effect is obviated using bias-temperature stress measurement. The proposed model successfully explains not only the phenomenon but also the thickness effect for the capacitance-voltage characteristics and the different turn-around voltages of the current density-voltage characteristics of the zirconium dielectrics. (C) 2002 American Institute of Physics.
A trap generation closed-form statistical model for intrinsic oxide breakdown
(2001-06-01)
Huang, HT
;
Chen, MJ
;
Su, CW
;
Chen, JH
;
Hou, CS
A trap generation statistical model with the trap sphere radius r as parameter has been newly formulated in closed-form for intrinsic breakdown of ultrathin oxides and, by incorporating the trap filling fraction p as the secondary parameter, can be practically useful in a manufacturing process. Experimental reproduction for different oxide thicknesses and areas has been achieved through the model. A certain criterion has readily been drawn from the model, with which the ultimate thickness limit for breakdown can be set.
Annealing effect on boron high-energy-ion-implantation-induced defects in
(2004-08-01)
Hsu, WC
;
Liang, MS
;
Chen, SC
;
Chen, MC
;
電子工程學系及電子研究所
In this work, we investigate the annealing effect on defects in Si induced by boron high-energy (1.5 MeV) ion implantation with respect to implantation dose (1.1 X 10(13) and 5 x 10(13) cm(-2)) as well as annealing scheme [rapid thermal annealing (RTA) and furnace annealing (FA)]. The higher dose implantation resulted in more serious degradation of the minority carrier generation lifetime in the implanted layers. Also, the degree of lifetime recovery by either RTA or FA was very limited with the higher dose implantation, presumably due to the presence of the implantation-induced dislocations. The degradation of the lifetime in the lower dose-implanted sample could be significantly recovered by the annealing process, particularly the RTA scheme; this is presumably because RTA has a better ability to reduce the implantation-induced interstitials.
Barrier characteristics of PECVD alpha-SiC : H dielectrics
(2001)
Chiang, CC
;
Wu, ZC
;
Wu, WH
;
Chen, MC
;
Ko, CC
This work investigates the thermal stability and barrier characteristics of three species of PECVD alpha-SiC:H dielectric films with dielectric constants between 3.5 and 5.4. It is found that the dielectric constant decreases with increasing content of carbon in the alpha-SiC:H film. All of the three specie's of alpha-SiC:H films are thermally stable at temperatures of up to 500degreesC. However, degraded barrier capability and moisture resistance were observed for the alpha-SiC:H film with a k value around 3.5, which has a C/Si atomic ratio of 0.875. This is presumably attributed to poorly crosslinked molecular structure and porosity enhancement by the abundant amount of carbon in the alpha-SiC:H film.
Characterization and modeling of edge direct tunneling (EDT) leakage in ultrathin gate oxide MOSFETs
(2001-06-01)
Yang, KN
;
Huang, HT
;
Chen, MJ
;
Lin, YM
;
Yu, MC
This paper examines the edge direct tunneling (EDT) of electron from n(+) polysilicon to underlying n-type drain extension in off-state n-channel MOSFET's having ultrathin gate oxide thicknesses (1.4-2.4 mm), It is found that for thinner oxide thicknesses, electron EDT is more pronounced over the conventional gate-induced-drain-leakage (GIDL), bulk band-to-band tunneling (BTBT), and gate-to-substrate tunneling, and as a result, the induced gate and drain leakage is better measured per unit gate width. A physical model is for the first time derived for the oxide field fox at the gate edge by accounting for electron subband in the quantized accumulation polysilicon surface. This model relates fox to the gate-to-drain voltage, oxide thickness, and doping concentration of drain extension, Once fox is known, an existing DT model readily reproduces EDT I-V consistently and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well.
Characterization of hot-hole injection induced SILC and related disturbs in flash memories
(2001-02-01)
Yih, CM
;
Ho, ZH
;
Liang, MS
;
Chung, SS
;
電子工程學系及電子研究所
In this paper, we have proposed a new method for the study of disturb failure mechanisms caused by stress induced leakage current (SILC) in source-side erased flash memories. This method is able to directly separate the individual components of SILC due to either carrier charging/disharging in the oxide or the positive charge/trap assisted electron tunneling into the floating gate, In addition, the present method is very sensitive with capability of measuring ultralow current (<10(-19) A), Results show that, at low oxide field, the disturb is mainly contributed by the so-called charging/disharging of carriers into/from the oxide due to the capacitance coupling effect. While at high oxide field, the positive charge/trap assisted electron tunneling induced floating-gate charge variation is the major cause of disturb failure.
Comparative study of physical and electrical characteristics of F- and C-doped low-K CVD oxides
(2001)
Wu, ZC
;
Shiung, ZW
;
Chiang, CC
;
Wu, WH
;
Chen, MC
This work makes a comparative study of physical and electrical properties between two species of inorganic low-K CVD oxides, namely F-doped FSG (fluorinated silicate glass, K=3.5) and C-doped OSG (organosilicate glass, K=2.9). It is found that FSG has a higher thermal stability (>600degreesC) than OSG (500degreesC) based on the results of 30 min thermal anneal in N-2 ambient. The degradation of the low-K property in OSG is predominately due to the thermal decomposition of methyl (CH3) groups at temperatures above 500degreesC, which are incorporated to reduce the density and polarizability of OSG. For the Cu-gated oxide-sandwiched low-K dielectric MIS capacitors, Cu permeation was observed in both FSG and OSG after the MIS capacitors were subjected to bias-temperature stressing (BTS) at 250 and 150degreesC, respectively, with an effective applied field of 0.8 MV/cm. It appeared that Cu drifted more readily in OSG than in FSG presumably because OSG has a more porous and less dense structure than FSG. The Cu penetration can be efficiently mitigated by a thin nitride dielectric barrier layer.
Detection of the defects induced by boron high-energy ion implantation of silicon
(2000-08-01)
Hsu, WC
;
Chen, MC
;
Liang, MS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A preferential chemical etching method was used to investigate the secondary defects induced in silicon by high-energy boron ion implantation followed by a rapid thermal anneal at 1000 degrees C for 30 s in N-2 ambient. The dislocation defects in silicon can be clearly delineated by the etchant of CrO3/HF mixing solution. Moreover, a band of striation corresponding To the region of dislocation defects can be observed from the cross-sectional view micrographs of scanning electron microscopy. For the high-energy boron ion implantation at a dose of 3 x 10(14) cm(-2) and energies of 0.5 to 2 MeV studied in this worst, the defect density is estimated to be in the order of 6 x 10(6) cm(-2). Furthermore, we found a close correlation between the depth profiles of the observed etching pits and that of the implanration-induced damage. (C) 2000 The Electrochemical Society. S0013-4651(00)01-011-9. All rights reserved.
Dielectric and barrier properties of spin-on organic aromatic low dielectric constant polymers FLARE and SiLK
(2001-06-01)
Wu, ZC
;
Shiung, ZW
;
Wu, RG
;
Liu, YL
;
Wu, WH
This work investigates the dielectric and barrier properties of two species of organic aromatic low dielectric constant (low-k) polymers, namely, FLARE and SiLK. Experimental results indicate that both of the low-k polymers exhibit acceptable thermal stability with respect to a thermal annealing at 400 degreesC for 8 h in an N-2 ambient. Moreover, they show a good dielectric barrier property against Cu penetration under bias-temperature stressing (BTS) at 150 degreesC with an applied effective field of 0.8 MV/cm. Nevertheless, an anomalous instability of the capacitance-voltage curve was observed for the first time under BTS. This finding is explained by the proposed model of stress induced dielectric polarization charges within these organic aromatic polymers. The polarization instability may seriously degrade the long term reliability of circuit operations. (C) 2001 The Electrochemical Society.
Edge hole direct tunneling in off-state ultrathin gate oxide p-channel MOSFETs
(2000)
Yang, KN
;
Huang, HT
;
Chen, MJ
;
Lin, YM
;
Yu, MC
This paper examines the edge direct tunneling (EDT) of hole from p(+) polysilicon to underlying p-type drain extension in off-state p-channel MOSFETs having ultrathin gate oxide thicknesses (1.2 - 2.2 nm). It is found that for thinner oxide thicknesses, hole EDT is more pronounced over the conventional GIDL and gate-to-channel tunneling, and as a result, the induced gate and drain leakage is better measured per unit gate width. A physical model accounting for heavy and light hole's subbands in the quantized accumulation polysilicon surface is built explicitly. This model consistently reproduces EDT I-V and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well.
Edge hole direct Tunneling leakage in ultrathin gate oxide p-channel MOSFETs
(2001-12-01)
Yang, KN
;
Huang, HT
;
Chen, MJ
;
Lin, YM
;
Yu, MC
This paper examines the edge direct tunneling (EDT) of holes from p(+) polysilicon to underlying p-type drain extensions in off-state p-channel MOSFETs having ultrathin gate oxides that are 1.2 nm-2.2 nm thick. It is for the first time found that for thinner oxides, hole EDT is more pronounced than both conventional gate-induced drain leakage (GIDL) and gate-to-channel tunneling. As a result, the induced gate and drain leakage is more accurately measured per unit gate width. Terminal currents versus input voltage are measured from a CMOS inverter with gate oxide thickness T-OX = 1.23 nm, exhibiting the impact of EDT in two standby modes. For the first time, a physical model is derived for the oxide field E-OX at the gate edge by accounting for the heavy and light holes' subbands in the quantized accumulation polysilicon surface. This model relates E-OX to the gate-to-drain voltage, oxide thickness, and doping concentration of the drain extension. Once E-OX is known, an existing direct tunneling (DT) model consistently reproduces EDT current-voltage (I-V), and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to hole EDT is projected.
Effects of base oxide in HfSiO/SiO2 high-k gate stacks
(2004)
Wu, WH
;
Chen, MC
;
Wang, MF
;
Hou, TH
;
Yao, LG
Electrical characteristics of HfSiO/SiO2 high-k gate stacks have been extensively explored with regard to the effects of base oxide. The flatband voltage shift in N/PMOS capacitors is independent of base oxide thickness, and the dielectric breakdown of the gate stacks is determined by base oxide. In addition, base oxide thickness has a great impact on device performance and charge trapping, presumably due to remote Coulomb scattering (RCS) in the HfSiO bulk layer and direct tunneling through the base oxide. Threshold voltage instability induced by charge trapping will be a major reliability concern for Hf-based high-k gate dielectrics in the future.
Effects of base oxide thickness and silicon composition on charge trapping in HfSiO/SiO(2) high-k gate stacks
(2005-08-01)
Wu, WH
;
Chen, MC
;
Tsui, BY
;
How, YT
;
Yao, LG
This work investigates the fundamentals of charge trapping and the effects of base oxide thickness and Si composition on charge trapping in HfSiO/SiO(2) high-k gate stacks using positive-bias temperature (PBT) stressing scheme. During the PBT stress, threshold voltage shift and saturation drain current degradation induced by charge trapping continue to grow and eventually become saturated, whereas the subthreshold swing and maximum transconductance remain unchanged. The extent of charge trapping increases with the decrease of base oxide thickness and Si composition in the HfSiO film, which can be explained by considering the channel-to-bulk tunneling time constant and the amount of neutral Hf-OH trapping centers in the HfSiO bulk layer. The power law dependence of saturation drain current degradation on the gate bias voltage indicates that charge trapping would become more significant if thin base oxide and low Si composition were employed in the further scaled HfSiO/SiO(2) high-k gate stacks.
Effects of base oxide thickness and silicon composition on charge trapping in HfSiO/SiO2 high-k gate stacks
(2005-08-01)
Wu, WH
;
Chen, MC
;
Tsui, BY
;
How, YT
;
Yao, LG
This work investigates the fundamentals of charge trapping and the effects of base oxide thickness and Si composition on charge trapping in HfSiO/SiO2 high-k gate stacks using positive-bias temperature (PBT) stressing scheme. During the PBT stress, threshold voltage shift and saturation drain current degradation induced by charge trapping continue to grow and eventually become saturated, whereas the subthreshold swing and maximum transconductance remain unchanged. The extent of charge trapping increases with the decrease of base oxide thickness and Si composition in the HfSiO film, which can be explained by considering the channel-to-bulk tunneling time constant and the amount of neutral Hf-OH trapping centers in the HfSiO bulk layer. The power law dependence of saturation drain current degradation on the gate bias voltage indicates that charge trapping would become more significant if thin base oxide and low Si composition were employed in the further scaled HfSiO/SiO2 high-k gate stacks.
Effects of O-2- and N-2-plasma treatments on copper surface
(2004-11-01)
Chiang, CC
;
Chen, MC
;
Li, LJ
;
Wu, ZC
;
Jang, SM
In this work, we investigate the effects of oxygen (O-2) and nitrogen (N-2) plasma treatments on the copper surface of aluminum/amorphous silicon-nitricarbide/copper (Al/alpha-SiCN/Cu) metal-insulator-metal (MIM) capacitors with respect to their leakage current and breakdown field. It is found that both the O-2- and N-2-plasma treatments have an adverse effect on the leakage current and breakdown field of MIM capacitors. The MIM capacitors with their Cu surfaces subjected to O-2- or N-2-plasma treatment exhibit a room-temperature leakage current density several orders of magnitude larger than that of the sample without plasma treatment at the same applied electric field. The room-temperature breakdown fields of the MIM capacitors with O-2- and N-2-plasma-treated Cu surfaces are 3.8 and 3.2 MV/cm, respectively, while that of the control sample without plasma treatment is 7.8MV/cm. The increased leakage currents and degraded breakdown fields of the O-2- and N-2-plasma-treated samples are attributed, respectively, to the presence of metastable Cu-O oxide and Cu-N azide at the Cu surfaces.
Effects of polysilicon gate doping concentration on plasma charging damage in ultrathin gate oxides
(2000-02-01)
Chen, CC
;
Lin, HC
;
Chang, CY
;
Huang, TY
;
Chien, CH
Effects of poly-gate doping concentration on plasma charging damage in ultrathin gate oxides were investigated. While the charge-to-breakdown (Q(bd)) value under gate injection stress polarity (-V-g) is independent of the doping concentration, eb, under substrate injection stress polarity (+V-g) shows a noticeable improvement with increasing doping concentration. However, our results show that plasma-induced oxide degradation is actually aggravated with increasing poly-gate doping concentration. These seemingly inconsistent observations can be explained by the lowering of plasma charging potential in the case of insufficient poly-gate doping. (C) 1999 The Electrochemical Society. S1099-0062(99)10-079-8. All rights reserved.
Electrical reliability issues of integrating low-K dielectrics with Cu metallization
(2000)
Wu, ZC
;
Shiung, ZW
;
Wang, CC
;
Fang, KL
;
Wu, RG
Electrical reliability issues of two organic aromatic low-K materials (K = 2.6 similar to 2.8) were investigated. Both materials show acceptable thermal stability and good dielectric barrier property against Cu penetration. C-V curve instability was observed under bias-temperature stress (BTS) for the first time. It can be explained by the model of stress induced dielectric polarization charges. This instability may be an issue of long term stability of circuits.