Browsing by Author "Liang, Sheng-Chuan"

Now showing 1 - 7 of 7

10GSamples/s, 4-bit, 1.2V, design-for-testability ADC and DAC in 0.13 mu m CMOS technology
(2007)
Liang, Sheng-Chuan
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Huang, Ding-Jyun
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Ho, Chen-Kang
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Hong, Hao-Chiao
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電控工程研究所
This paper demonstrates a 10GS/s, 4-bit, flash analog-to-digital converter (ADC) and current-steering digital-to-analog converter (DAC) pair for the design or advanced serial-link transceivers. Current mode logic (CML) gates are used to alleviate the severe power bouncing. The active feedback amplifiers, CML, and wave-pipelining technique help achieve the ultimate 10 GHz sampling rate. A design-for-testability circuit using the digital loop-back scheme is added to address the difficulty of at-speed measurements. The experimental results show that the cascaded ADC and DAC pair achieves a 27.3 dBc spurious-free dynamic range and a 25.0 dB signal-to-noise ratio with the 1.11 GHz, -1 dBm stimulus. It corresponds to an ENOB of 3.86 bits. The test chip totally consumes 420 mW from a 1.2V supply. The areas of the ADC and DAC are 0.1575 mm(2) and 0.0636 mm(2), respectively in 0.13 mu m CMOS technology.
A Built-in-Self-Test I sigma-Delta ADC Prototype
(2009-06-01)
Hong, Hao-Chiao
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Liang, Sheng-Chuan
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Song, Hong-Chin
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電控工程研究所
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Institute of Electrical and Control Engineering
This paper presents a built-in-self-test (BIST) I - pound Delta ADC prototype. The BIST circuity uses the proposed modified controlled sine wave fitting (CSWF) procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. Compared with conventional Fast Fourier Transform (FFT) analysis, neither complex CPU/DSP nor bulky memory is required. The added BIST circuitry is purely digital and the hardware overhead is as low as 11.9 K gates. A prototype comprising the second-order design-for-digital-testability I - pound Delta modulator chip and an FPGA board which implements the digital functions is used to demonstrate the effectiveness of the BIST design. Measurement results show that the SNDR difference between conventional FFT analysis and the proposed BIST design of the standard -aEuro parts per thousand 6 dBFS, 1 KHz tone test is only 0.3 dB. Furthermore, the tested dynamic range values by both methods are the same. The proposed BIST implementation achieves the advantages of compact hardware, high test accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.
A cost effective BIST second-order Sigma-A-modulator
(2008)
Hong, Hao-Chiao
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Liang, Sheng-Chuan
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Song, Hong-Chin
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電控工程研究所
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Institute of Electrical and Control Engineering
This paper demonstrates a cost effective built-in-self-test (BIST) E-A modulator prototype. The BIST prototype is composed of a design-for-digital-testability second-order E-A modulator chip and a FPGA which implements the digital BIST functions. The BIST system is based on the modified control sine wave fitting (MCSWF) procedure. Different from the con- ventional analysis method using Fast Fourier Transform (FFT), this implementation requires neither any parallel multiplier nor complex CPU/DSP and bulky memory. Measurement results show that the BIST prototype gives a signal-to-noise-and-distortion ratio (SNDR) result of 74.3 dB which is within 0.3 dB comparing with the FFT counterpart. The proposed BIST implementation achieves the advantages of compact hardware, high accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.
A cost effective output response analyzer for Sigma-Delta modulation based BIST systems
(2006)
Hong, Hao-Chiao
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Liang, Sheng-Chuan
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電控工程研究所
;
Institute of Electrical and Control Engineering
A cost effective output response analyzer (ORA) for Sigma-Delta modulation based BIST systems is presented. Instead of using Fast Fourier Transform (FFT) to derive the signal-to-noise-and-distortion ratio (SNDR) infrequency domain, the proposed ORA using the modified controlled sine wave fitting procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. It requires neither parallel multiplier nor complex CPU/DSP and bulky memory thus has a low cost. A second-order design-for-digital-testability Sigma-Delta modulator is used as the circuit under test example. Simulation results show that the SNDR differences between conventional FFT analysis and the proposed ORA have a mean and standard deviation of 0.64 dB and 0.36 dB respectively. The cost effectiveness and satisfying accuracy features make it suitable for embedded BIST applications.
A Decorrelating Design-for-Digital-Testability Scheme for Sigma - Delta Modulators
(2009-01-01)
Hong, Hao-Chiao
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Liang, Sheng-Chuan
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電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a novel decorrelating design-for-digital-testability (D(3)T) scheme for Sigma - Delta modulators to enhance the test accuracy of using digital stimuli. The input switched-capacitor network of the modulator under test is reconfigured as two or more subdigital-to-charge converters in the test mode. By properly designing the digital stimuli, the shaped noise power of the digital stimulus can be effectively attenuated. As a result, the shaped noise correlation as well as the modulator overload issues are alleviated, thus improving the test accuracy. A second-order Sigma - Delta modulator design is used as an example to demonstrate the effectiveness of the proposed scheme. The behavioral simulation results showed that, when the signal level of the stimulus tone is less than - 5 dBFS, the signal-to-noise ratios obtained by the digital stimuli are inferior to those obtained by their analog counterparts of no more than 1.8 dB. Circuit-simulation results also demonstrated that the D(3)T scheme has the potential to test moderate nonlinearity. The proposed D(3)T scheme has the advantages or achieving high test accuracy, low circuit overhead, high fault observability, and the capability of conducting at-speed tests.
A Digitally Testable Sigma - Delta Modulator Using the Decorrelating Design-for-Digital-Testability
(2011-03-01)
Liang, Sheng-Chuan
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Hong, Hao-Chiao
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電機工程學系
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Department of Electrical and Computer Engineering
This paper demonstrates a digitally testable second-order Sigma - Delta modulator. The modulator under test (MUT) employs the decorrelating design-for-digital-testability (D(3)T) scheme to provide two operation modes: the normal mode and the digital test mode. In the digital test mode, the input switched-capacitor network of the D(3)T modulator is reconfigured as two sub-digital-to-charge converters (sub-DCCs). Each of the sub-DCCs accepts a Sigma - Delta modulated bit-stream as its test stimulus. By repetitively inputting the DCCs with the same Sigma - Delta modulated bit-stream but with different delays, the DCCs incorporates with the integrator to generate the analog stimulus in the digital test mode. The analog stimulus is analogous to the result of filtering the bit-stream with a two-nonzero-term FIR decorrelating term. Consequently, the D(3)T MUT suffers less from the undesired shaped noise of the digital stimuli, and achieves better digital test accuracy. Measurement results show that the digital tests present a peak signal-to-noise-and-distortion ratio (SNDR) of 80.1 dB at an oversampling ratio of 128. The SNDR results of the digital tests differ from their conventional analog counterparts by no more than 2 dB except for the -3.2 dBFS test. The analog hardware overhead of the D(3)T MUT only consists of 13 switches.
A Low-Cost Output Response Analyzer for the Built-in-Self-Test Sigma-Delta Modulator Based on the Controlled Sine Wave Fitting Method
(2009)
Hung, Shao-Feng
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Hong, Hao-Chiao
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Liang, Sheng-Chuan
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper proposes I low-cost output response analyzer (ORA) for the built-in-self-test (BIST) Sigma-Delta ADC based on the controlled sine wave fitting (CSWF) method. The ADC under test (AUT) is composed of a design-for-digital-testability (DfDT) second-order E-A modulator and a decimation filter. The CSWF BIST procedure requests in ORA to accept the output of the AUT and calculates the offset, the amplitude of the stimulus tone response, and the total-harmonic-distortion-and-noise (THD+N) power in three successive BIST steps respectively. Each BIST step needs all accumulator to conduct the specified BIST function. By sharing an accumulator for every BIST step, the proposed ORA design contains only 1.9k gates without loss of computational accuracy. The hardware is only 34% of the original design. Simulation results show that the proposed ORA presents accurate SNDR results for the 1 kHz tests.