Browsing by Author "Liang, Yu-Jie"

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All Digitally Controlled Linear Voltage Regulator with PMOS Strength Self-Calibration for Ripple Reduction
(2015)
Kuo, Yi-Ping
;
Huang, Po-Tsang
;
Wu, Chung-Shiang
;
Liang, Yu-Jie
;
Chuang, Ching-Te
In this paper, an all-digitally controlled linear voltage regulator is proposed for ultra-low-power event-driven sensing platforms using a PMOS strength self-calibration technique. The voltage regulator generates the output voltage from 0.43V to 0.55V in steps of 30mV with a supply voltage of 0.6V. Against PVT and loading current variations, the PMOS strength self-calibration circuitry utilizes a voltage-detected coarse tune and a timing-detected fine tune for output ripple reduction. The coarse tune is designed to suppress the output voltage within the fine-tune region via a comparator-based error detector. Accordingly, the fine tune block detects the PMOS turn-on ratio in a specific time window for further reducing the output ripple. This linear voltage regulator is implemented using TSMC 65nm LP CMOS process. The simulation results show the best improvement of ripple reduction by 81%. Moreover, ns-order voltage transition time and the best ( lowest) FOM of 0.76 pA.s can be realized.
Multiple Output Switched Capacitor DC-DC Converter with Capacitor Sharing for Sensor-Fusion Platforms
(2016)
Liang, Yu-Jie
;
Chen, Po-Ilung
;
Lu, Hung-Pin
;
Chu, Yuan-Hua
;
Hwang, Wei
In this paper, a multiple output switched capacitor (SC) DC-DC converter with capacitor sharing technique is proposed for event-driven energy-efficient sensor-fusion platforms. The converter is able to convert 1.2V supply voltage to five different output voltages ranging from 0.44V to 2.2V to power different building blocks in the system. A part of the flying capacitor can be shared between five SC cells according to the loading condition to reduce the chip area. With capacitor sharing concept, 36% of on-chip metal-insulator-metal (MIM) capacitor can be reduced. The proposed switched capacitor DC-DC converter is implemented by TSMC 90nm CMOS process. The simulation results show the converter achieves 80% maximum conversion efficiency with less than 20mV output ripple.