Browsing by Author "Liao, Chia-Chun"

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Benefit of NMOS by Compressive SiN as Stress Memorization Technique and Its Mechanism
(2010-04-01)
Liao, Chia-Chun
;
Chiang, Tsung-Yu
;
Lin, Min-Chen
;
Chao, Tien-Sheng
;
電子物理學系
In this letter, we certify that the compressive SiN capping layer has more potential than the tensile layer for fabrication using the stress memorization technique to enhance NMOS mobility. The mechanism that we have proposed implies that the conventional choice of the capping layer should bemodulated from the point of view of stress shift rather than using the highest tensile film.
Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals
(2010-08-01)
Chiang, Tsung-Yu
;
Wu, Yi-Hong
;
Ma, William Cheng-Yu
;
Kuo, Po-Yi
;
Wang, Kuan-Ti
In this paper, silicon-oxide-nitride-oxide-semiconductor (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method with multilevel and 2-b/cell operation have been successfully demonstrated. The proposed in situ Si-NC deposition method exhibits the advantages of low cost, simplicity, and compatibility with modern IC processes. SONOS memories with embedded Si-NCs exhibit a significantly improved performance with a large memory window (> 5.5 V), low operating voltage (P/E voltage: V(g) = 6 V, V(d) = 7 V and V(g) = -7 V, V(d) = 10 V, respectively), greater tolerable gate and drain disturbance (V(t) shift < 0.2 V), negligible second-bit effect, high P/E speed (after programming time = 10 mu s with a 2-V shift of V(t) under V(g) = V(d) = 6 V operation), good retention time (> 10(8) s for 13% charge loss), and excellent endurance performance (after 10(4) P/E cycles with a memory window of 3 V).
Effects of Channel Width and Nitride Passivation Layer on Electrical Characteristics of Polysilicon Thin-Film Transistors
(2011-11-01)
Liao, Chia-Chun
;
Lin, Min-Chen
;
Chiang, Tsung-Yu
;
Chao, Tien-Sheng
;
電子物理學系
SiN passivation layers were found to yield better performance, suppress the kink effect, and improve the gate leakage current and gate-induced drain leakage (GIDL) of polysilicon thin-film transistors (TFTs). The SiN passivation layers deposited under different deposition conditions possess different characteristics due to their varying passivation effect. A physical mechanism is proposed to explain the double-hump phenomenon induced by incomplete trap passivation. Based on the analysis of width dependence, the better performance of the samples with SiN passivation layers was attributed not only to radical passivation of the defect states but also to radical passivation of preexisting defects in the gate oxide. Furthermore, using SiN passivation layers improves immunity to positive gate bias stress, negative gate bias stress, and hot-carrier stressing. Moreover, the manufacturing processes are simple (without the long processing time plasma treatment requires) and compatible with TFT processes.
Hydrogen Instability Induced by Postannealing on Poly-Si TFTs
(2012-06-01)
Liao, Chia-Chun
;
Lin, Min-Chen
;
Chao, Tien-Sheng
;
電子物理學系
;
Department of Electrophysics
This brief investigates hydrogen instability induced by postannealing. Results show that using a SiN capping layer can prevent the release of hydrogen from a polycrystalline-silicon channel. However, removing this SiN capping layer allows the hydrogen release during postannealing, and the resulting device performance becomes comparable to that of the control sample. Hydrogen release reduces the immunity of PBTI and NBTI. Two possible mechanisms can explain the increased preexisting defects associated with hydrogen release, which affects the NBTI and PBTI.
Impact of Strain Layer on Gate Leakage and Interface-State for nMOSFETs Fabricated by Stress-Memorization Technique
(2011)
Liao, Chia-Chun
;
Lin, Min-Chen
;
Chiang, Tsung-Yu
;
Chao, Tien-Sheng
;
電子物理學系
This paper investigates the impact of stress memorization on the interface-state for n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETS). We found that both the initial component of the deposited capping layer and the H released during annealing affected interface-state passivation. The annealed stress is responsible for degraded gate-leakage characteristics. Based on electrical performance and gate leakage, an initial compressive layer of SiN performs better than an initial tensile layer for the stress-memorization technique process. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3506399] All rights reserved.
Impacts of the Underlying Insulating Layers on the MILC Growth Length and Electrical Characteristics
(2012-02-01)
Liao, Chia-Chun
;
Lin, Min-Chen
;
Liu, Shao-Xuan
;
Chao, Tien-Sheng
;
電子物理學系
This letter investigates the impacts of proximity layers on metal-induced lateral crystallization (MILC). The underlying insulating layers not only affect the MILC growth length but also influence the electrical characteristics. Based on the comparison among the underlying insulating layers, SiN is unsuitable to be an underlying insulating layer because of concerns regarding the crystallization condition. This letter proposes three reasonable mechanisms, including the gettering of Ni, intrinsic stress, and the involvement of hydrogen to enhance the understanding of the impacts of proximity layers.
MILC-TFT With High-kappa Dielectrics for One-Time-Programmable Memory Application
(2009-09-01)
Chiang, Tsung-Yu
;
Ma, Ming-Wen
;
Wu, Yi-Hong
;
Kuo, Po-Yi
;
Wang, Kuan-Ti
In this letter, for the first time, one-time-programmable (OTP) memory fabricated on the low-temperature poly-Si p-cbannel thin-film transistor (TFT) with metal-induced lateral-crystallization channel layer and high-kappa dielectrics is demonstrated. The state of this OTP memory can be identified by the scheme of gate-induced drain leakage current measurement. The OTP-TFT memory has good electrical characteristics in terms of low threshold voltage V(th) similar to -0.78 V, excellent subthreshold swing similar to 105 mV/dec, low operation voltage, faster programming speeds, and excellent reliability characteristics.
Novel 2-Bit/Cell Wrapped-Select-Gate SONOS TFT Memory Using Source-Side Injection for NOR-Type Flash Array
(2012-06-01)
Wang, Kuan-Ti
;
Hsueh, Fang-Chang
;
Lu, Yu-Lun
;
Chiang, Tsung-Yu
;
Wu, Yi-Hong
This letter is the first to successfully demonstrate the 2-bit/cell wrapped-selected-gate (WSG) SONOS thin-film transistor (TFT) memory using source-side injection (SSI). Because of the higher programming efficiency of SSI, a memory window of approximately 3 V can be easily achieved in 10 mu s and 30 ms for the program and erase modes, respectively. In addition, we performed an excellent 2-bit/cell distinguish margin for 3-V memory window in WSG-SONOS TFT memory. The optimal reliability of the endurance and data retention tests can be executed by adjusting the applied voltage appropriately.
Physical Mechanism of High-Programming-Efficiency Dynamic-Threshold Source-Side Injection in Wrapped-Select-Gate SONOS for NOR-Type Flash Memory
(2009-11-01)
Wang, Kuan-Ti
;
Chao, Tien-Sheng
;
Chiang, Tsung-Yu
;
Wu, Woei-Cherng
;
Kuo, Po-Yi
For the first time, a programming mechanism for conventional source-side injection (SSI) (normal mode), substrate-bias enhanced SSI (body mode), and dynamic-threshold SSI (DTSSI) (DT mode) of a wrapped-select-gate SONOS memory is developed with 2-D Poisson equation and hot-electron simulation and programming characteristic measurement for NOR Flash memory. Compared with traditional SSI, DTSSI mechanisms are determined in terms of lateral acceleration electric field and programming current (I(PGM)) in the neutral gap region, resulting in high programming efficiency. Furthermore, the lateral electric field intersects the vertical electric field, indicating that the main charge injection point is from the end edge of the gap region close to the word gate.
Reliability Analysis of Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors
(2012-08-01)
Wu, Yi-Hong
;
Lin, Je-Wei
;
Lu, Yi-Hsien
;
Kuo, Rou-Han
;
Yen, Li-Chen
"In this paper, a reliability analysis of symmetric Vertical-channel Ni-SAlicided poly-Si thin-film transistors (VSA-TFTs) is performed for the first time. First, we compare the drain-induced barrier-lowering effect (DIBL) of VSA-TFTs. The VSA-TFTs with thinner gate oxide thickness, an offset structure, and a longer floating n(+) region have better immunity to DIBL. Second, VSA-TFTs with a longer floating n(+) region also have better immunity under hot-carrier (HC) stress and self-heating (SH) stress. However, VSA-TFTs with a shorter floating n(+) region also have better immunity to positive gate bias (PGB) stress. Consequently, in order to optimize reliability characteristics, including SH stress, HC stress, and PGB stress, it is necessary to modulate the length of the floating n(+) region. Third, the PGB stress, rather than SH stress or HC stress, becomes a major issue for VSA-TFTs under the stress bias below 4 V. In other words, PGB stress will dominate the degradation behaviors when the stress bias is not high enough to achieve SH stress and HC stress. Finally, the worst degradation condition of VSA-TFTs under HC stress, similar to that of most TFT devices, occurs when the stress of V-G is less than half of V-D"