Browsing by Author "Liao, Chien-Hui"

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An Online Thermal-Constrained Task Scheduler for 3D Multi-Core Processors
(2015)
Liao, Chien-Hui
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Wen, Charles H. -P.
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Chakrabarty, Krishnendu
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資訊工程學系
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電信工程研究所
Hotspots occur frequently in 3D multi-core processors (3D-MCPs) and they can adversely impact system reliability and lifetime. Moreover, frequent occurrences of hotspots lead to more dynamic voltage and frequency scaling (DVFS), resulting in degraded throughput. Therefore, a new thermal-constrained task scheduler based on thermal-pattern-aware voltage assignment (TPAVA) is proposed in this paper. By analyzing temperature profiles of different voltage assignments, TPAVA pre-emptively assigns different operating-voltage levels to cores for reducing temperature increase in 3D-MCPs. Moreover, the proposed task scheduler integrates a vertical-grouping voltage scaling (VGVS) strategy that considers thermal correlation in 3D-MCPs. Experimental results show that, compared with two previous methods, the proposed task scheduler can respectively lower hotspot occurrences by 47.13% and 53.91%, and improve throughput by 6.50% and 32.06%. As a result, TPAVA and VGVS are effectively for reducing occurrences of hotspots and optimizing throughput for 3D-MCPs under thermal constraints.
An Online Thermal-Pattern-Aware Task Scheduler in 3D Multi-Core Processors
(2017-12-01)
Liao, Chien-Hui
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Wen, Charles H. -P.
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電機工程學系
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電信工程研究所
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Department of Electrical and Computer Engineering
Hotspots occur frequently in 3D multi-core processors (3D-MCPs), and they may adversely impact both the reliability and lifetime of a system. We present a new thermally constrained task scheduler based on a thermal-pattern-aware voltage assignment (TPAVA) to reduce hotspots in and optimize the performance of 3D-MCPs. By analyzing temperature profiles of different voltage assignments, TPAVA pre-emptively assigns different initial operating-voltage levels to cores for reducing temperature increase in 3D-MCPs. The proposed task scheduler consists of an on-line allocation strategy and a new voltage-scaling strategy. In particular, the proposed on-line allocation strategy uses the temperature-variation rates of the cores and takes into two important thermal behaviors of 3D-MCPs that can effectively minimize occurrences of hotspots in both thermally homogeneous and heterogeneous 3D-MCPs. Furthermore, a new vertical-grouping voltage scaling (VGVS) strategy that considers thermal correlation in 3D-MCPs is used to handle thermal emergencies. Experimental results indicate that, when compared to a previous online thermally constrained task scheduler, the proposed task scheduler can reduce hotspot occurrences by approximately 66% (71%) and improve throughput by approximately 8% (2%) in thermally homogeneous (heterogeneous) 3D-MCPs. These results indicate that the proposed task scheduler is an effective technique for suppressing hotspot occurrences and optimizing throughput for 3D-MCPs subject to thermal constraints.
Diagnosing Multiple Byzantine Open-Segment Defects Using Integer Linear Programming
(2011-12-01)
Kao, Chen-Yuan
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Liao, Chien-Hui
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Wen, Charles H. -P.
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Faulty behaviors of open-segment defects are non-deterministic due to the Byzantine effect induced by the physical circuit layout. It is the test pattern and difficult for traditional ATPGs to manifest the corresponding faulty effect. Therefore, we propose a three-stage diagnosis approach for finding multiple open-segment defects. Stage one applies path tracing to help extract candidate fault sites from error outputs of failing patterns. An ILP solver in stage two effectively enumerates all fault combinations when considering fault candidates and simulation responses simultaneously. During stage three, fault simulation with support of physical information is responsible for identifying true open-segment defects by pruning false cases. Experimental results show good resolutions (only 1.7X and 1.5X total numbers of segments on average under 1,000 random and 5-detect patterns, respectively) for all ISCAS'85 circuits with 2-5 randomly-injected open-segment defects.
Dynamic Voltage Assignment for Thermal-Constrained Task Scheduler on 3D Multi-Core Processors
(2015)
Liao, Chien-Hui
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Lin, Yu-Ze
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Wen, Charles H. -P.
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傳播研究所
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資訊工程學系
Thermal-constrained task scheduler for throughput optimization on 3D multi-core processors (3D-MCPs) has been studied extensively. Most task scheduler focused on thermal-aware task allocation to reduce hotspots, thereby maximizing throughput under thermal constraints. Rather than focusing on the thermal-aware task allocation as previous work does, this work targets on the voltage assignment. In this paper, dynamic voltage assignment is proposed to pre-emptively assign different voltage levels to cores frequently for reducing temperature increase in 3D-MCPs. Experimental results show that two previous task schedulers integrated with the proposed dynamic voltage assignment can lower hotspot occurrences by 62.31% and 59.09%, and improve throughput by 18.28% and 18.35%, respectively. As a result, task schedulers integrated with the proposed dynamic voltage assignment can be more effective to reduce occurrences of hotspots and optimize throughput for 3D-MCPs under thermal constraints.
Flow-and-VM Migration for Optmizing Throughput and Energy in SDN-based Cloud Datacenter
(2013-01-01)
Lin, Wei-Chu
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Liao, Chien-Hui
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Kuo, Kuan-Tsen
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Wen, Charles H-P.
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電機資訊學士班
Minimizing energy consumption and improving performance in datacenters are critical to cost-saving for cloud operators, but traditionally, these two optimization objectives are treated separately. Therefore, this paper presents an unified solution combining two strategies, flow migration and VM migration, to maximize throughput and minimize energy, simultaneously. Traffic-aware flow migration (FM) is first incorporated in dynamic reroute (DENDIST), evolving into DENDIST-FM, in a software-defined network (SDN) for improving throughput and avoiding congestion. Second, given energy and topology information, VM migration (ETA-VMM) can help reduce traffic loads and meanwhile save energy. Our experimental result indicates that compared to previous works, the proposed method can improve throughput by 42.5% on average with only 2.2% energy overhead. Accordingly, the unified flow-and-VM migration solution has been proven effective for optimizing throughput and energy in SDN-based cloud datacenters.
Online task scheduler in 3D-MCPs with TADVA
(2018-03-01)
Liao, Chien-Hui
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Wen, Charles Hung-Pin
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資訊工程學系
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電信工程研究所
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Department of Computer Science
Hotspots occur frequently in three-dimensional (3D) multi-core processors (3D-MCPs), and they may adversely impact both the reliability and lifetime of a system. The authors present dynamic-voltage-assignment (DVA) strategies that reduce hotspots in and optimise the performance of 3D-MCPs by pre-emptively selecting voltages among low-power and high-performance operating modes. The proposed DVA strategies can be employed in online, thermally constrained task schedulers. Three DVA strategies, random DVA, thermal-aware DVA (TADVA) and TADVA2.0, are proposed to reduce the temperature increase in 3D-MCPs by pre-emptively and dynamically estimating the optimum VAs for all cores in the processor during runtime once the chip begins operating. In particular, TADVA2.0 uses the temperature-variation rates of the cores and takes into account two important thermal behaviours of 3D-MCPs that can effectively limit the temperature increase in 3D-MCPs. Experimental results indicate that, when compared with two previous online thermally constrained task schedulers, the proposed task scheduler with their novel DVA strategy can reduce hotspot occurrences by approximate to 60% and improve throughput by approximate to 8%. These results indicate that the proposed TADVA2.0 strategy is an effective technique for suppressing hotspot occurrences and optimising throughput for 3D-MCPs subject to thermal constraints.
SVM-Based Dynamic Voltage Prediction for Online Thermally Constrained Task Scheduling in 3-D Multicore Processors
(2018-06-01)
Liao, Chien-Hui
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Wen, Charles H. -P.
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電機工程學系
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電信工程研究所
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Department of Electrical and Computer Engineering
Hotspots occur frequently in 3-Dmulticore processors (3D-MCPs) and they may adversely impact the reliability of the system and its lifetime. We present support-vector-machine (SVM)-based dynamic voltage assignment (SVMDVA) strategy to select voltages among low-power and high-performance operating modes for reducing hotspots and optimizing performance in 3D-MCPs. The proposed SVMDVA can be employed in online, thermally constrained task schedulers. First, we revealed two different thermal regions of 3D-MCPs and extract different key features of these regions. Based on these key features, SVM models are constructed to predict the thermal behavior and the best operation mode of 3D-MCPs during runtime. SVMDVA using SVM models with monitoring workload and temperature behavior can effectively limit the temperature increase in 3D-MCPs. This is extremely important for accurately predicting the thermal behavior and providing the optimum operating condition of 3D-MCPs to achieve the best system performance. Experimental results show that SVMDVA is an effective technique for reducing hotspot occurrences (57.19%) and increasing throughput (25.41%) for 3D-MCPs.
Thermal-Constrained Task Scheduling on 3-D Multicore Processors for Throughput-and-Energy Optimization
(2015-11-01)
Liao, Chien-Hui
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Wen, Charles H. -P.
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
Thermal-constrained task scheduler for throughput optimization on 3-D multicore processors (3-D MCPs) has been studied extensively. However, these throughput-optimized strategies often ignore energy consumption and overuse thermal simulations. Therefore, in this brief, a new strategy named thermal-aware mapping and VoltagE scaling (TAMVES) is proposed to optimize throughput and energy consumption while satisfying thermal constraints (in terms of both peak temperature and temperature gradient) simultaneously. Layer-by-layer task-to-core mapping and thermal-and-energy-aware voltage scaling are incorporated in TAMVES to reduce peak temperature and temperature gradient without extensive thermal simulation. Furthermore, idle time slots are also utilized by voltage scaling for minimizing energy consumption. Our experimental results show that under thermal constraints, TAMVES outperforms a previous work (3-D Wave) by 35.30% averagely on throughput. In addition, TAMVES that features three-order faster speed under timing constraints outperforms 3-D Wave for saving 51.17% more energy and reducing 8.37% more peak temperature and 5.67% more temperature gradient. As a result, TAMVES has proven itself an effective task scheduler that optimizes throughput and energy on 3-D MCPs under thermal constraints.