Browsing by Author "Liao, Po-Hsiang"

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A Unique Approach to Generate Self-Aligned SiO2/Ge/SiO2/SiGe Gate-Stacking Heterostructures in a Single Fabrication Step
(2015-05-19)
Lai, Wei-Ting
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Yang, Kuo-Ching
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Hsu, Ting-Chia
;
Liao, Po-Hsiang
;
George, Thomas
We report a first-of-its-kind, unique approach for generating a self-aligned, gate-stacking heterostructure of Ge quantum dot (QD)/SiO2/SiGe shell on Si in a single fabrication step. The 4-nm-thick SiO2 layer between the Ge QD and SiGe shell fabricated during the single-step process is the result of an exquisitely controlled dynamic balance between the fluxes of oxygen and silicon interstitials. The high-quality interface properties of our "designer" heterostructure are evidenced by the low interface trap density of as low as 2-4 x 10(11) cm(-2) eV(-1) and superior transfer characteristics measured for Ge-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Thanks to the very thin interfacial SiO2 layer, carrier storage within the Ge QDs with good memory endurance was established under relatively low-voltage programming/erasing conditions. We hope that our unique self-aligned, gate-stacking heterostructure provides an effective approach for the production of next-generation, high-performance Ge gate/SiO2/SiGe channel MOSFETs.
Designer Ge Quantum-Dot Phototransistors for highly-integrated, broadband optical interconnects
(2016)
Kuo, Ming-Hao
;
Chien, Chung-Yen
;
Liao, Po-Hsiang
;
Lai, Wei-Ting
;
Li, Pei-Wen
We report high-responsivity Ge quantum dots (QDs) MOS phototransistors as on-chip transducers for highly-integrated, broadband Si-based optical interconnects. Self-organized heterostructure of Ge-QD/SiO2/Si-channel is fabricated in a single step through selective oxidation of SiGe nano-pillars over a Si3N4 buffer layer on Si substrates. Dark current densities (10(-7)A/mm(2)), photocurrent-to-dark current ratio (similar to 10(7)) and photoresponsivities (>10 A/W), external quantum efficiency (similar to 240%), and response time (1.4ns) are measured on the Ge-QD phototransistors under 850 nm illumination. Detection wavelength is tunable from near infrared to near ultraviolet by reducing the QD size from 90 to 7 nm, and the optimal photoresponsivity is tailored by the QD size and effective thickness of gate dielectrics.
Gate-stack engineering for self-aligned Ge-gate/SiO2/SiGe-channel Insta-MOS devices
(2015)
Lai, Wei-Ting
;
Yang, Kuo-Ching
;
Liao, Po-Hsiang
;
George, Thomas
;
Li, Pei-Wen
We reported a first-of-its-kind, self-aligned gate-stack heterostructure of Ge-nanoshpere-gate/SiO2/SiGechannel on Si in a single-step approach through selective oxidation of a SiGe nano-patterned pillar over a Si3N4 buffer layer on Si substrate. Good tunability on the Ge-nanoshpere size, SiO2 thickness, and SiGe-shell thickness provides a practically-achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices with size-tunable Ge gates, SiO2 gate oxide, and SiGe channels. Detailed interfacial morphologies and structural properties between the Ge nanosphere/SiO2 and SiO2/SiGe-channel were examined using transmission electron microscopy, energy dispersive x-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Both Al/SiO2/Genanospheres and NiGe/SiO2/SiGe MOS capacitors exhibit quite low interface trap densities of 3-5x10(11) cm(-2)eV(-1), which is beneficial for advanced Ge MOS applications.
Gate-Stack Engineering for Self-Organized Ge-dot/SiO2/SiGe-Shell MOS Capacitors
(2016-02-11)
Lai, Wei-Ting
;
Yang, Kuo-Ching
;
Liao, Po-Hsiang
;
George, Tom
;
Li, Pei-Wen
We report the first-of-its-kind, self-organized gate-stack heterostructure of Ge-dot/SiO2/SiGe-shell on Si fabricated in a single step through the selective oxidation of a SiGe-nanopatterned pillar over a Si3N4 buffer layer on a Si substrate. Process-controlled tunability of the Ge-dot size (7.5-90 nm), the SiO2 thickness (3-4 nm), and the SiGe-shell thickness (2-15 nm) have been demonstrated, enabling a practically achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices. Detailed morphologies, structural, and electrical interfacial properties of the SiO2/Ge-dot and SiO2/SiGe interfaces were assessed using transmission electron microscopy, energy dispersive X-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Notably, NiGe/SiO2/SiGe and Al/SiO2/Ge-dot/SiO2/SiGe MOS capacitors exhibit low interface trap densities of as low as 3-5 x 10(11) cm(-2) eV(-1) and fixed charge densities of 1-5 x 10(11) cm(-2), suggesting good-quality SiO2/SiGe-shell and SiO2/Ge-dot interfaces. In addition, the advantage of having single-crystalline Si1-xGex shell (x > 0.5) in a compressive stress state in our self-aligned gate-stack heterostructure has great promise for possible SiGe (or Ge) MOS nanoelectronic and nanophotonic applications.
Self-Organized Ge Nanospherical Gate/SiO2/Si0.15Ge0.85-Nanosheet n-FETs Featuring High ON-OFF Drain Current Ratio
(2019-01-01)
Liao, Po-Hsiang
;
Peng, Kang-Ping
;
Lin, Horng-Chih
;
George, Thomas
;
Li, Pei-Wen
We reported experimental fabrication and characterization of Si0.15Ge0.85 n-MOSFETs comprising a gate-stacking heterostructure of Ge-nanospherical gate/SiO2/Si0.15Ge0.85-nanosheet on SOI (100) substrate in a self-organization approach. This unique gate-stacking heterostructure is simultaneously produced in a single oxidation step as a consequence of an exquisitely controlled dynamic balance between the concentrations of oxygen, Si, and Ge interstitials at 900 degrees C. Process-controlled tunability of nanospherical gate of 60-100 nm in diameter, gate oxide thickness of 3 nm, and Si0.15Ge0.85 nanosheet with compressive strain of -2.5% was achieved. Superior gate modulation is evidenced by subthreshold slope of 150 mV/dec and I-ON/I-OFF > 5 x 10(8) (I-OFF < 10(-6) mu A/mu m and I-ON > 500 mu A/mu m) measured at V-G = + 1V, V-D = + 1 V, and T = 80 K for our device with channel length of 75 nm.