Browsing by Author "Liao, Sheng-Hui"

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A 1 V 175 mu W 94.6 dB SNDR 25 kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques
(2018-01-01)
Liao, Sheng-Hui
;
Wu, Jieh-Tsorng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 2-1 MASH switched-capacitor delta-sigma modulator was fabricated using a 65 nm CMOS technology. We constantly alternate the circuit configurations of its internal integrators to optimize power consumption. The integrators are accelerated only when they are in crucial integration cycle. Operating at 5 MS/s sampling rate, this chip consumes 175 mu W from a 1 V supply. Assuming a 25 kHz signal bandwidth, it achieves 96.1 dB SNR, 94.6 dB SNDR, and 98.5 dB DR. Its active area is 1.13 x 0.34 mm(2).
A 1-V 175-mu W 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques
(2019-09-01)
Liao, Sheng-Hui
;
Wu, Jieh-Tsorng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 2-1 multistage noise-shaping (MASH) switched-capacitor (SC) delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. We developed two separate segmented integration techniques to implement the first two integrators in the DSM. The techniques use both an inverter (IVT)-based opamp and a source-coupled-pair (SCP)-based opamp to relay the charge integration operation. This increases performance while saving power. The first integrator also operates more slowly during output sampling to further reduce power consumption. Operating at a 5-MS/s sampling rate, this chip consumes 175 mu W from a 1-V supply. For a 25-kHz signal bandwidth, it achieves a 96.1-dB signal-to-noise ratio (SNR), a 94.6-dB signal-to-noise-plus-distortion ratio (SNDR) and a 98.5-dB dynamic range (DR). Its active area is 1.13 x 0.34 mm(2).