Browsing by Author "Liao, Ta-Chuan"

Now showing 1 - 20 of 23

A New Charge-Trap-Engineered Memory Device with Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) Structure for LTPS-TFT-Based Applications
(2010)
Liao, Ta-Chuan
;
Wu, Chun-Yu
;
Chen, Sheng-Kai
;
Yu, Ming H.
;
Kang, Tsung-Kuei
For the first time, a new Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) LTPS-TFT-based charge-trapping memory integrated on a gate-all-around field-enhanced-nanowire architecture was demonstrated. The vacuum, simply formed by an in-situ encapsulation, substituted for the traditional tunneling oxide. Due to the lowest-k and empty properties of vacuum, SONVAS features electric field enhancement in tunneling layer and immunity against the creation of interface traps and the charge trapping in the damaged tunneling oxide during P/E cycling, resulting in the much-improved P/E efficiency and reliability, respectively. Therefore, such vacuum-introduced SONVAS memory device with process simplicity is very suitable for the future system-on-panel (SOP) and 3D-stacking flash applications.
A Novel LTPS-TFT-Based Charge-Trapping Memory Device with Field-Enhanced Nanowire Structure
(2009)
Liao, Ta-Chuan
;
Chen, Sheng-Kai
;
Yu, Ming H.
;
Wu, Chun-Yu
;
Kang, Tsung-Kuei
A novel gate-all-around low-temperature poly-Si (LIPS) thin-film transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory with field-enhanced nanowire (FEN) structure has been proposed to improve the program and erase (P/E) performance. Each nanowire inherently had three sharp corners fabricated simply by sidewall spacer formation to obtain high local electric fields. The field-enhanced carrier tunneling via such a structure led to faster PIE speed and wider memory window for the FEN-TFT SONOS as compared to the conventional planar (CP) counterpart. The improvement was also further verified with the simulation results. Such a high-performance FEN-TFT SONOS memory with process simplicity is very suitable for future system-on-panel (SOP) applications.
A Novel Polysilicon Field-Enhanced Nanowire Thin-Film Transistor with the TiN-Hafnia-Nitride-Vacuum-Silicon (THNVAS) Structure for Nonvolatile Memory Applications
(2012-07-01)
Wu, Chun-Yu
;
Liao, Ta-Chuan
;
Liu, Yen-Ting
;
Yu, Ming H.
;
Cheng, Huang-Chung
A novel poly-Si field-enhanced nanowire (FEN) TFT memory with the TiN-hafnia-nitride-vacuum-silicon (THNVAS) structure fabricated simply via a sidewall spacer formation has been presented. The THNVAS devices with superior memory performance were demonstrated by introducing the hafnia as blocking oxide and the vacuum, the lowest-k in nature, as tunneling layer. According to the simulation results, the memory device with oxide/nitride/vacuum gate dielectric exhibited a higher local electric-field of 4.72 x 10(7) V/cm as compared to 2.55 x 10(7) V/cm for the conventional oxide/nitride/oxide counterpart. In addition, the electric-field of tunneling layer could be further increased to 7.06 x 10(7) V/cm while the blocking oxide was substituted for hafnia. The experimental data showed that THNVAS possessed a greater threshold voltage shift of 3.75 V in 10 ms at V-GS = 12 V, whereas the shift only 2.5 V for THNOS ones. These considerable improvements for THNVAS devices could be attributed to the evident field enhancement across the vacuum tunneling layer. Furthermore, owing to the empty feature of vacuum tunneling layer, the THNVAS demonstrated much-improved endurance performance and preferable data retention property. Hence, such excellent characteristics of THNVAS will be an attractive nonvolatile memory for future system-on-panel and 3-D Flash applications.
A novel self-aligned field induced drain polycrystalline silicon thin film transistor fabricated by using a selective side etch process
(2007)
Liao, Ta-Chuan
;
Wu, Chun-Yu
;
Chien, Feng-Tso
;
Tsai, Chun-Chien
;
Chen, Hsiu-Hsin
A novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with vacuum gaps has been proposed and fabricated only with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH4-based passivation oxide under the vacuum process chamber. Experimental results reveal that the proposed T-Gate poly-Si TFTs have excellent electrical performance, which has maximum on-off current ratio of 4.6 x 10(7), and off-state leakage current at V-GS = -10 V and V-DS = 5V of about 100 times less than that of the conventional one. These improvements are attributed to the additional undoped offset region and the vacuum gap, which reduce the maximum electric field at drain junction while the sub-gate maintains the on-current. Therefore, such a T-Gate poly-Si TFT is very suitable for the applications and manufacturing in active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs).
A poly-Si thin-film transistor with the in situ vacuum gaps under the T-shaped-gated electrode
(2006)
Liao, Ta-Chuan
;
Wu, Chun-Yu
;
Chien, Feng-Tso
;
Tsai, Chun-Chien
;
Chen, Hsiu-Hsin
A T-shaped-gated (T-gate) poly-Si thin-film transistor (TFT) with symmetric vacuum gaps has been proposed and fabricated simply with a selective-etching technique and an in situ vacuum encapsulation. The proposed TFT has demonstrated a higher maximum on-off current ratio and superior reliability compared to the conventional TFTs. This is attributed to the resulting offset region and vacuum gap to reduce the off-state leakage current and improve the hot-carrier reliability, while the extra subgate serves to induce an inversion layer at the offset region to maintain the on current during the on state. Therefore, such a T-gate poly-Si TFT is very suitable for manufacturing and applications in active-matrix flat panel electronics. (c) 2006 The Electrochemical Society.
Advanced gate-all-around fin-like poly-Si TFTs with multiple nanowire channels
(2008)
Tu, Shih-Wei
;
Liao, Ta-Chuan
;
Lin, Wei-Kai
;
Liu, Cheng-Chin
;
Tai, Ya-Hsiang
The gate-all-around (GAA) fin-like poly-Si TFTs (FinTFTs) with multiple nanowire channels (MNCs) have been fabricated using a simple process to demonstrate high performance electrical characteristics. The fin-like nanowire (NW) channel with high body thickness-to-width ratio (T-Fin/W-Fin), approximately equals to one, was realized only with a sidewall-spacer formation. The unique suspending MNCs were also achieved to build the GAA structure. By the way, the GAA-MNC Fin TFTs showed outstanding three-dimensional gate controllability and excellent electrical characteristics, which revealed a high ON/OFF current ratio (>10(8)), a low threshold voltage, a steep subthreshold swing, a near-free drain-induced barrier lowering and a good reliability. Therefore, such the high-performance GAA-MNC FinTFTs are vet-v suitable for the applications in the system-on-panel (SOP) and three-dimensional (3D) circuits.
Effect of Nitrogen Plasma Treatment on Electrical Characteristics for Pd Nanocrystals in Nonvolatile Memory
(2010-08-01)
Kang, Tsung-Kuei
;
Liao, Ta-Chuan
;
Lin, Cheng-Li
;
Wu, Wen-Fa
;
電子工程學系及電子研究所
Pd nanocrystals (NCs) are successfully embedded in a TaN/SiO(2)/HfAlO/Si structure The initial memory window increases at a higher rate with increasing fabrication temperature of Pd NCs compared with the linear variation of Pd NC density, which is related to the thermally induced neutral traps in the HfAlO film around Pd NCs After manufacturing a TaN/SiO(2)/Pd NCs/HfAlO/Si/Al structure, the subsequent N(2) plasma treatment is conducted at 300 degrees C for 3 min The number of leakage current paths in the SiO(2) blocking layer adjacent to TaN is clearly reduced, but that of leakage current paths in SiO(2)/HfAlO around Pd NCs is slightly increased owing to the thermal stress The thermally induced neutral traps in the HfAlO film around the Pd NCs can be passivated by nitrogen atoms, which leads to the improvement of the final memory window for the Pd NC samples fabricated at 600-700 degrees C However, the intrinsic traps in the HfAlO film play an important role in memory characteristic and the final memory window is reduced by thermal densification for the Pd NC samples fabricated at 500 degrees C (C) 2010 The Japan Society of Applied Physics
Field enhancement of omega-shaped-gated poly-Si TFT SONOS memory fabricated by a simple sidewall spacer formation
(2010-05-01)
Wu, Chun-Yu
;
Liao, Ta-Chuan
;
Yu, Ming-H
;
Chen, Sheng-Kai
;
Tsai, Chung-Min
A novel omega-shaped-gated (Omega-Gate) poly-Si thin-film-transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices fabricated with a simple process have been proposed for the first time. The Omega-Gate structure inherently covered two sharp corners manufactured simply via a side-wall spacer formation. Due to the sharp corner geometry, the local electric fields across the tunneling oxide could be enhanced effectively, thus improving the memory performance. Based on this field enhanced scheme, the Omega-Gate TFT SONOS revealed excellent program/erase (P/E) efficiency and larger memory window as compared to the conventional planar (CP) counterparts. In addition, owing to the better gate controllability, the Omega-Gate TFT SONOS also exhibited superior transistor performance with a much higher on-current, smaller threshold voltage, and steeper subthreshold swing. Therefore, such an Omega-Gate TFT SONOS memory is very promising for the embedded flash on the system-on-panel applications. (C) 2010 Elsevier Ltd. All rights reserved.
Gate-All-Around Poly-Si TFTs With Single-Crystal-Like Nanowire Channels
(2011-09-01)
Kang, Tsung-Kuei
;
Liao, Ta-Chuan
;
Lin, Chia-Min
;
Liu, Han-Wen
;
Wang, Fang-Hsing
The gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with single-crystal-like nanowire (NW) channels (SCLNCs) are demonstrated and characterized. Via the nanoscale nitride spacer, the Si NW can be easily transformed within one crystalline grain of the two-shot sequential-lateral-solidification poly-Si film. As compared with the planar ones, the GAA-SCLNC TFTs showed more excellent characteristics. The results clearly show that the variations of device characteristics can be reduced by increasing the numbers of NWs in the channels and an average mobility above 410 cm(2)/V . s with a low standard deviation can be achieved for the GAA-SCLNC TFTs with 20-NW channels.
Gate-all-around polycrystalline-silicon thin-film transistors with self-aligned grain-growth nanowire channels
(2012-02-27)
Liao, Ta-Chuan
;
Kang, Tsung-Kuei
;
Lin, Chia-Min
;
Wu, Chun-Yu
;
Cheng, Huang-Chung
In this letter, gate-all-around (GAA) polycrystalline silicon thin-film transistors (TFTs) with self-aligned grain-growth channels were fabricated using excimer laser crystallization (ELC) on a recessed-nanowire (RN) structure. Via the RN structure constructed by a simple sidewall-spacer formation, location-controlled nucleation and volume-confined lateral grain growth within the RN body during ELC process have been demonstrated with only one perpendicular grain boundary in each nanowire channel. Because of the high-crystallinity channel together with GAA operation mode, the proposed GAA-RN TFTs show good device integrity of lower threshold voltage, steeper subthreshold slope, and higher field-effect mobility as compared with the conventional planar counterparts. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.3691184]
High Sensitivity of Dry-Type Nanowire Sensors With High-k Dielectrics for pH Detection via Capillary Atomic Force Microscope Tip Coating Technique
(2012-09-01)
Cheng, Huang-Chung
;
Wu, Chun-Yu
;
Hsu, Po-Yen
;
Wang, Chao-Lung
;
Liao, Ta-Chuan
Dry-type poly-Si nanowire pH sensors with high-k dielectrics have been demonstrated with the aid of novel focus ion beam engineered capillary atomic force microscopy (C-AFM) tip. By means of this C-AFM tip coating technique, the relatively few testing solutions can be transferred onto the surface of a nanowire, preventing the sensor device from the immersion in the liquid and therefore suppressing the possible leakage current from the testing solution. As compared with the TEOS SiO2, the pH sensors comprising Al2O3, TiO2, and HfO2 high-k materials exhibit the better sensitivities due to their enhanced capacitances. The best sensitivity (138.7 nA/pH) and linearity (99.69%) for a HfO2 dielectric can be ascribed to the higher k value and larger bandgap with respect to the Al2O3 and TiO2, accordingly. Consequently, the C-AFM tip coating technique incorporating with HfO2 dielectric suggests the potential for the detection of a minute quantity of biomedicines.
High-performance solid-phase crystallized polycrystalline silicon thin-film transistors with floating-channel structure
(2008-04-01)
Chang, Chia-Wen
;
Deng, Chih-Kang
;
Chang, Che-Lun
;
Liao, Ta-Chuan
;
Lei, Tan-Fu
High-performance solid-phase crystallized polycrystalline silicon thin-film transistors with a floating-channel active region (FC poly-Si TFTs) are proposed in this study. A high-quality poly-Si channel film accompanied by a larger grain size and fewer microstructural defects could be obtained. Compared with the conventional poly-Si TFTs (CN poly-Si TFTs), the fabricated FC poly-Si TFTs exhibit superior electrical characteristics, including lower threshold voltage, higher field-effect mobility, and lower trap state density. These electrical performance improvements could be attributed to the fact that the a-Si film with a floating-channel structure can relieve the stress generated from the crystallization process accompanying the trap state density reduction and grain size enhancement. In addition, the FC poly-Si TFTs also exhibit improved hot-carrier stress immunity due to the reduced weak Si-H bonds from fewer grain boundaries in the poly-Si channel. Therefore, the proposed FC poly-Si TFTs can be easily fabricated by conventional solid-phase crystallization, and suitable for future high-performance flat-panel display applications.
Improved characteristics for Pd nanocrystal memory with stacked HfAlO-SiO(2) tunnel layer
(2011-07-01)
Kang, Tsung-Kuei
;
Liu, Han-Wen
;
Wang, Fang-Hsing
;
Lin, Cheng-Li
;
Liao, Ta-Chuan
Stacked HfAlO-SiO(2) tunnel layers are designed for Pd nanocrystal nonvolatile memories. For the sample with 1.5 nm-HfAlO/3.5 nm-SiO(2) tunnel layer, a smaller initial memory window is obtained compared to the sample with 3.5 nm-HfAlO/1.5 nm-SiO(2) tunnel layer. Owing to the thermally induced traps in HfAlO-SiO(2) films are located at a farther distance from the Si substrate and more effective blocking of charge leakage by asymmetric tunnel barrier, a larger final memory window and better retention characteristic can be obtained for Al/blocking oxide SiO(2)/Pd NC5/1.5 nm-HfAlO/3.5 nm-SiO(2)/Si structure. A N(2) plasma treatment can further improve the memory characteristics. Better memory characteristics can be obtained for Pd-nanocrystal-based nonvolatile memory with an adequate thickness ratio of HfAlO to SiO(2). (C) 2011 Elsevier Ltd. All rights reserved.
Improved characteristics for Pd nanocrystal memory with stacked HfAlO-SiO2 tunnel layer
(2011-07-01)
Kang, Tsung-Kuei
;
Liu, Han-Wen
;
Wang, Fang-Hsing
;
Lin, Cheng-Li
;
Liao, Ta-Chuan
Stacked HfAlO-SiO2 tunnel layers are designed for Pd nanocrystal nonvolatile memories. For the sample with 1.5 nm-HfAlO/3.5 nm-SiO2 tunnel layer, a smaller initial memory window is obtained compared to the sample with 3.5 nm-HfAlO/1.5 nm-SiO2 tunnel layer. Owing to the thermally induced traps in HfAlO-SiO2 films are located at a farther distance from the Si substrate and more effective blocking of charge leakage by asymmetric tunnel barrier, a larger final memory window and better retention characteristic can be obtained for Al/blocking oxide SiO2/Pd NC5/1.5 nm-HfAlO/3.5 nm-SiO2/Si structure. A N-2 plasma treatment can further improve the memory characteristics. Better memory characteristics can be obtained for Pd-nanocrystal-based nonvolatile memory with an adequate thickness ratio of HfAlO to SiO2. (C) 2011 Elsevier Ltd. All rights reserved.
Improving electrical performance of the scaled low-temperature poly-Si thin film transistors using vacuum encapsulation technique
(2008)
Lin, Wei-Kai
;
Liao, Ta-Chuan
;
Wu, Chun-Yu
;
Tu, Shih-Wei
;
Liu, Yen-Ting
A novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with in-situ vacuum gaps has been proposed and fabricated with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH4-based passivation oxide under the vacuum process chamber. The proposed T-Gate poly-Si TFT has demonstrated to suppress the short-channel effects by simulated and measured characterization. It is attributed to the undoped offset region and vacuum gap to reduce the maximum electric field at drain Junction..
Novel Dielectric-Engineered Trapping-Charge Poly-Si-TFT Memory With a TiN-Alumina-Nitride-Vacuum-Silicon Structure
(2011-08-01)
Wu, Chun-Yu
;
Liu, Yen-Ting
;
Liao, Ta-Chuan
;
Yu, Ming H.
;
Cheng, Huang-Chung
High-performance poly-Si-TFT-based TiN-alumina-nitride-vacuum-silicon (TANVAS) trapping-charge memory has been demonstrated utilizing high-k blocking oxide and vacuum tunneling layer for the first time. In particular, the vacuum, lowest k in nature, was introduced to replace the traditional tunneling oxide. Furthermore, the alumina high-k blocking oxide was applied to upgrade the electric field across the tunneling layer. Based on the enlarged k-value difference between the blocking and tunneling layers, the TANVAS featured considerable field enhancement across the tunneling layer, thus much improving the program/erase efficiencies. In addition, owing to the suppression of defect creation in the tunneling layer, the TANVAS also exhibited superior retention characteristics. These excellent memory characteristics of TANVAS are therefore promising for the 3-D Flash and system-on-panel applications.
Novel gate-all-around poly-Si TFTs with multiple nanowire channels
(2008-08-01)
Liao, Ta-Chuan
;
Tu, Shih-Wei
;
Yu, Ming H.
;
Lin, Wei-Kai
;
Liu, Cheng-Chin
The novel gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with multiple nanowire channels (MNCs) have been, for the first time, fabricated using a simple process to demonstrate high-performance electrical characteristics and high immunity to short-channel effects (SCEs). The nanowire channel with high body-thickness-to-width ratio (T(Fin)/W(Fin)), which is approximately equal to one, was realized only with a sidewall-spacer formation. Moreover, the unique suspending MNCs were also achieved to build the GAA structure. The resultant GAA-MNC TFTs showed outstanding three-dimensional (3-D) gate controllability and excellent electrical characteristics, which revealed a high on/off current ratio (> 10(8)), a low threshold voltage, a steep subthreshold swing, a near-free drain-induced barrier lowering, as well as an excellent SCE suppression. Therefore, such high-performance GAA-MNC TFTs are very suitable for applications in system-on-panel and 3-D circuits.
Novel junctionless silicon-oxide-nitride-oxide-silicon memory devices with field-enhanced poly-Si nanowire structure
(2015-08-01)
Chou, Chia-Hsin
;
Chan, Wei-Sheng
;
Wu, Chun-Yu
;
Lee, I-Che
;
Liao, Ta-Chuan
In this work, a novel gate-all-around (GAA) low-temperature poly-Si (LTPS) junctionless (JL) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory device with a field-enhanced nanowire (NW) structure has been proposed to improve the programing/erasing (P/E) performance. Each nanowire has three sharp corners fabricated by a sidewall spacer formation technique to obtain high local electrical fields. Owing to the higher carrier concentration in the channel and the high local electrical field from the three sharp corners, such a JL SONOS memory device exhibits a significantly enhanced P/E speed, a larger memory window, and better data retention properties than a conventional inversion mode NW-channel memory device. (C) 2015 The Japan Society of Applied Physics
Novel Omega-Shaped-Gated TFT SONOS Memory
(2009)
Liao, Ta-Chuan
;
Chen, Sheng-Kai
;
Kang, Tsung-Kuei
;
Hsu, Pang-Yu
;
Lin, Chia-Min
A novel omega-shaped-gated (Omega-Gate) polycrystalline-silicon thin-film transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory with field-enhanced nanowire (FEN) structure has been proposed to improve the program and erase (P/E) performance. Each nanowire inherently had twin sharp corners fabricated simply by sidewall spacer formation to obtain high local electric fields. The field-enhanced carrier tunneling via such a structure led to faster P/E speed and wider memory window for the Omega-Gate SONOS as compared to the conventional planar (CP) counterpart. Such an Omega-Gate-TFT SONOS memory using a simple process is very suitable for future system-on-panel applications.
Passivation-Induced Subthreshold Kink Effect of Ultrathin-Oxide Low-Temperature Polycrystalline Silicon Thin Film Transistors
(2011-07-01)
Tsai, Mon-Chin
;
Liao, Ta-Chuan
;
Lee, I-Che
;
Cheng, Huang-Chung
;
電子工程學系及電子研究所
Polycrystalline silicon thin-film transistors (poly-Si TFTs) with an ultrathin electron cyclotron resonance plasma-oxidized gate oxide have been fabricated. These ultrathin gate oxide poly-Si TFTs demonstrate better gate controllability and short-channel effect suppression, as compared with conventional thick-gate oxide poly-Si TFTs. A subthreshold kink effect has been observed in these ultrathin gate oxide poly-Si TFTs after NH(3) plasma treatment for the first time. The ultrathin oxide will limit the diffusion of plasma radicals, resulting in plasma radical pileup along the channel width, causing this subthreshold kink effect. The kink effect will be less significant in devices with a narrow channel width as the current flow associated with the corners of the device will dominate over the flat-plate region.