Browsing by Author "Liao, Te-Wen"

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All-Digital Fast-Locking Pulsewidth-Control Circuit With Programmable Duty Cycle
(2013-06-01)
Su, Jun-Ren
;
Liao, Te-Wen
;
Hung, Chung-Chih
;
電機工程學系
;
Department of Electrical and Computer Engineering
This paper proposes an all-digital fast-locking pulsewidth-control circuit with programmable duty cycle. In comparison with prior state-of-the-art methods, our use of two delay lines and a time-to-digital detector allows the pulsewidth-control circuit to operate over a wide frequency range with fewer delay cells, while maintaining the same level of accuracy. This paper presents a new duty-cycle setting circuit that calculates the desired output duty cycle without the need for a look-up table. The circuit was fabricated under the two-stage matrix converter 0.18-mu m CMOS process. Results show that the proposed circuit performs well for an input operating frequency ranging from 200 to 600 MHz, and an input duty cycle ranging from 30% to 70%. It achieves a programmable output duty cycle ranging from 31.25% to 68.75% in increments of 6.25%.
Delay-Line Based Fast-Locking All-Digital Pulsewidth-Control Circuit with Programmable Duty Cycle
(2012)
Su, Jun-Ren
;
Liao, Te-Wen
;
Hung, Chung-Chih
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposes an all-digital fast-locking pulsewidth-control circuit with programmable duty-cycle. In comparison with prior art, our use of two delay lines and a time-to-digital detector allows the pulsewidth-control circuit to operate over a wide frequency range with fewer delay cells, while maintaining the same level of accuracy. This study presents a new duty-cycle setting circuit that calculates the desired output duty cycle without the need for a look-up table. Results show that the proposed circuit performs well for an input operating frequency ranging from 200 to 600MHz, and an input duty cycle ranging from 30 to 70%. It achieves a programmable output duty cycle ranging from 31.25 to 68.75% in increments of 6.25%.
Low-Spur Technique For Integer-N Phase-Locked Loop
(2012)
Liao, Te-Wen
;
Su, Jun-Ren
;
Hung, Chung-Chih
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we presents a low-spur phase locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator (VCO) in order to reduce the reference spur at the output of the PLL. A new random clock generator is presented to perform a random selection of phase frequency detector (PFD) control for charge pump at locked state. The proposed frequency synthesizer was fabricated in TSMC 0.18-mu m CMOS process. The PLL has achieved the phase noise of -105 dBc/Hz at 1MHz offset frequency and reference spurs below -72dBc.
Random Pulsewidth Matching Frequency Synthesizer With Sub-Sampling Charge Pump
(2012-12-01)
Liao, Te-Wen
;
Chen, Chia-Min
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Su, Jun-Ren
;
Hung, Chung-Chih
;
電機工程學系
This paper presents a fast locking phase-locked loop (FLPLL) system with reference-spur reduction techniques exploiting random pulsewidth matching and a sub-sampling charge pump. Through the randomization and average of the pulsewidth and the reduction of current mismatch, the frequency synthesizer can reduce the ripples on the control voltage of the voltage-controlled oscillator in order to reduce the reference spur at the output of the phase-locked loop. A random clock generator is used to perform a random selection control. The loop bandwidth of the system can be adjusted by the control voltage so as to reduce the locking time. To demonstrate the effectiveness of the proposed spur-reduction techniques, a 2.5 GHz to 2.7 GHz FLPLL was designed and fabricated using a TSMC 90-nm CMOS process. The proposed circuit can achieve a phase noise of - 114 dBc/Hz at an offset frequency of 1 MHz and reference spurs below - 74 dBc.
Ring-VCO Based Low Noise and Low Spur Frequency Synthesizer
(2013)
Liao, Te-Wen
;
Su, Jun-Ren
;
Hung, Chung-Chih
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a low phase-noise phase locked loop (PLL) system with a Multi-Phase Over-Sampling Charge Pump (MPOSCP) for wireless applications. The low phase-noise frequency synthesizer reduces ripples and noise on the control voltage of the ring voltage-controlled oscillator (VCO) as a means to control in-band noise at the output of the PLL. An MPOSCP is proposed to perform multi-phase over-sampling control for the charge pump (CP) in locked state. The proposed frequency synthesizer was fabricated using the TSMC 90-nm CMOS process. The prototype occupies 0.046mm2 active area, the reference frequency is 27 MHz, and the output frequency is 432 MHz with the total power consumption of 7 mW. The PLL achieved phase noise below - 100 dBc/Hz from 15 Hz to 100 kHz with the reference spurs below - 48 dBc.
Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD
(2013-03-01)
Liao, Te-Wen
;
Su, Jun-Ren
;
Hung, Chung-Chih
;
電機工程學系
;
Department of Electrical and Computer Engineering
This brief presents a low-spur phase-locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator to reduce the reference spur at the output of the PLL. A novel random clock generator is presented to perform the random selection of the phase frequency detector control for the charge pump in locked state. The proposed frequency synthesizer was fabricated in a TSMC 0.18-mu m CMOS process. The proposed PLL achieved phase noise of -93 dBc/Hz with a 600-kHz offset frequency and reference spurs below -72 dBc.
Sub-Sampling Charge Pump and Random Pulsewidth Matching Technique for Frequency Synthesizer
(2013)
Liao, Te-Wen
;
Su, Jun-Ren
;
Hung, Chung-Chih
;
交大名義發表
;
National Chiao Tung University
This paper presents a frequency synthesizer system with random pulsewidth matching technique and a sub-sampling charge pump. Through the randomization and average of the pulsewidth and the reduction of current mismatch, the frequency synthesizer can reduce the ripples on the control voltage of the voltage-controlled oscillator in order to reduce the reference spur at the output of the phase-locked loop. A random clock generator is used to perform a random selection control. To demonstrate the effectiveness of the proposed spur-reduction techniques, a 2.5GHz to 2.7 GHz FLPLL was designed and fabricated using a TSMC 90nm CMOS process. The proposed circuit can achieve a phase noise of - 114 dBc/Hz at an offset frequency of 1 MHz and reference spurs below - 74 dBc.