Browsing by Author "Liao, Yen-Chin"

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A (21150,19050) GC-LDPC Decoder for NAND Flash Applications
(2019-03-01)
Liao, Yen-Chin
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Lin, Chien
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Chang, Hsie-Chia
;
Lin, Shu
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電子工程學系及電子研究所
In this paper, a (21150, 19050) globally-coupled low-density parity check (GC-LDPC) code designed for NAND flash memories is presented. The proposed LDPC code comprises three disjoint subcodes which can be decoded independently. This highly structural parity check matrix contributes to efficient decoder implementation and flexible decoding flow control. Moreover, a two-phase local/global decoding procedure optimized for the proposed GC-LDPC code is introduced. Scenarios of collaborative decoding that leverages the special code structures are discussed. In the proposed decoder architecture, the pipelined processing elements with scheduling are employed to reduce the critical path and decoding latency as well. Implemented in UMC 65 nm process, the post-layout simulation shows a maximum decoding throughput of 432 Gb/s with the chip area 3.376 mm(2).
A 1.86mJ/Gb/Query Bit-Plane Payload Machine Learning Processor in 90nm CMOS
(2018-01-01)
Ku, Fang-Ju
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Wu, Tung-Yu
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Liao, Yen-Chin
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Chang, Hsie-Chia
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Wong, Wing Hung
This paper presents an implementation of an energy efficient hit-plane payload design for machine learning processor. The proposed architecture facilitates high parallelism and high data bandwidth and thus improves the model learning/training time of machine learning algorithms. By assembling multiple bits as a bit-plane and enlarging query parallelism with a central compare-Hag updater, data processing parallelism can be increased. Binary sequential partition (BSP), a fast density estimation algorithm capable of dealing with high dimensional data sets, is realized. Fabricated in 90nm IP9M CMOS process, the processing rate can achieve 16.9 Gb/sec with 8 queries for data dimension D=210. The test chip integrates 64 counting cells and provides 5 modes with power consumptions of 1.86mJ/Gb per Query.
A 3.46 Gb/s (9141,8224) LDPC-based ECC scheme and on-line channel estimation for Solid-State Drive Applications
(2015)
Ho, Kin-Chu
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Chen, Chih-Lung
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Liao, Yen-Chin
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Chang, Hsie-Chia
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Lee, Chen-Yi
As the reliability of NAND Flash memory keeps degrading, Low-Density Parity-Check (LDPC) codes are widely proposed to extend the endurance of Solid State Drive (SSD). However, implementing powerful decoding algorithm such as soft min-sum algorithm with high decoding speed comes along with higher hardware cost. To achieve efficient hardware cost, we propose a multi-strategy ECC scheme which consists of modified gradient descent bit-flipping (MGDBF), hard min-sum, and soft min-sum decoders. The MGDBF decoder aims to correct most of the erroneous codewords with advantages of high decoding throughput and low hardware cost, while the soft min-sum decoder is targeted to correct codewords with large number of errors under moderate decoding throughput and reasonable hardware cost. In addition, we propose a bi-sectional channel estimation technique which enables on-line estimation of distribution to generate accurate soft information for LDPC decoding with low complexity. The ECC codec and the complete Toggle DDR 1.0 NAND interface control circuits are integrated and fabricated in 90nm CMOS process. The throughput of proposed MGDBF decoder achieves 3.46 Gb/s which satisfies the throughput requirement of both toggle DDR 1.0 and 2.0 NAND interfaces.
A ISS-Length Full Code Rate 333Mbps 1.08mm(2) Radix-4 Hybrid-Trellis Thrbo Decoder with Zero Patching for 3GPP LTE-A
(2018-01-01)
Chang, Po-Hsun
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Lin, Chen-Yang
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Sun, Chia-Hsiang
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Liao, Yen-Chin
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Chang, Hsie-Chia
Decoding high code rate Thrbo codes by their reciprocal dual trellis has been shown to be potentially beneficial in implementation due to the simpler trellis structures. However, reciprocal dual trellis decoders' complexity grows significantly when the code rate is less than 1/2. Further, designing a multi-code rate reciprocal dual trellis decoder is even more challenging if periodical puncturing patterns is not always available. In this paper, a radix-4 hybrid-trellis LTE-A turbo decoder with a controller switching between the conventional trellis and the reciprocal dual trellis is presented. To accommodate all the rates defined in LTE-A, a zero patching scheme is proposed to create the periodical puncturing patterns required by the reciprocal dual trellis decoding. The implementation of the proposed decoder supports all the code rates, from 1/3 to 0.95, and all the 188 block lengths. Fabricated in TSMC TN28HPM process, the post-layout simulations show the proposed decoder could achieve 333Mbps at 6 iterations under 263MHz operating frequency. The core area is 1.08 mm(2), and the decoder draws 295.57 mW of power with energy efficiency of 0.148(nJ/bitJiter).
A self-compensation fixed-width booth multiplier and its 128-point FFT applications
(2006)
Huang, Hong-An
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Liao, Yen-Chin
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Chang, Hsie-Chia
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a method for compensating the truncation error of fixed-width Booth multipliers which keep the input and the output the same bit-width. The truncated part that produces the carry-out bits is replaced with a carry-estimation equation. In order to reduce the truncation error, different input-width multipliers will have different carry-estimation equations. Simulation results show that our self-compensation method can lead to 85% reduction of truncation errors while compared with direct-truncated multipliers, as well as 40% reduction in area of a multiplier while compared with traditional Booth multipliers. In contrast with the 128-point fast fourier transform (FFT) using traditional Booth multipliers, our approach has 10% area reduction but only 1dB SQNR loss.
Adjusted Robust Soliton Distribution (ARSD) with Reshaped Ripple Size for LT Codes
(2013)
Yen, Kuo-Kuang
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Liao, Yen-Chin
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Chen, Chih-Lung
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Chang, Hsie-Chia
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電子工程學系及電子研究所
In this work, we improve the performance of robust Soliton distribution (RSD) for LT codes by reshaping its expected ripple size. Our goal is to make the ripple size as close to a constant theta k as possible during BP decoding process, where 0 < theta <= 1 is called ripple size ratio (RSR) and k is the total number of input symbols. We only adjust the proportion of degree 1, degree 2 and the maximum existing degree in RSD to minimize the mean squared error between the expected ripple size and the constant theta k. In addition, we develop upper and lower bounds of RSR as well as an indicator for choosing RSD. Simulation results show that by carefully choosing RSR, the adjusted RSD (ARSD) is able to outperform RSD in terms of successful decoding rate. Compared to RSD, ARSD also reduces the average overhead needed to decode all k input symbols.
Data Analysis and Prediction for NAND Flash Decoding Status
(2017-01-01)
Liao, Yen-Chin
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Huang, Ching-Hui
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Zeng, Cloud
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Chang, Hsie-Chia
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電子工程學系及電子研究所
This paper investigates the feasibility of predicting the NAND flash decoding status by machine learning algorithms. The memory system can handle the future decoding failure in advance according to the prediction results so that to relieve the penalties. Several data preprocessing techniques to improve the accuracy are addressed. A thorough analysis flow is given and the experimental results show significant improvements. Incorporating with proper memory error handling schemes, a 34% improvement in throughput can be achieved.
Design of LT Code Degree Distribution with Profiled Output Ripple Size
(2015)
Yen, Kuo-Kuang
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Liao, Yen-Chin
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Chang, Hsie-Chia
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
LT codes, a candidate for next-generation forward error correction (FEC) scheme, draws great attention due to its low encoding/decoding complexity and capacity-approaching properties. Especially for wireless applications in fast-changing environments, adaptive degree distribution is a possible solution to balance the trade-off between LT codes\' efficiency and robustness. A fast mapping from attributes in the decoding process to degree distribution is required for realizing adaptive degree distribution. This study presents a reverse mapping from the expected ripple size to degree distributions. The basic idea is to minimize the error between a predetermined curve mu (rho) and the expected ripple size R (Omega (x); rho) of a target degree distribution Omega (x), where rho is the number of decoded input symbols. By converting the code degree design into a pure optimization problem, it is possible to design LT codes with constraints from performance requirements to complexity issues. Applying sequential quadratic programming, a ripple-based distribution (RBD) is presented as a feasible design example. Simulation results show that, as compared to robust Soliton distribution (RSD) and previous studies, RBD is able to reduce the transmission overhead as well as the encoding and decoding complexity by at least 31.2% and 25.4%, respectively.(1)
Early-pruned K-best sphere decoding algorithm based on radius constraints
(2008)
Wu, Yi Hsuan
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Liu, Yu Ting
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Chang, Hsiu-Chi
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Liao, Yen-Chin
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Chang, Hsie-Chia
A technique to prune the paths for K-best sphere decoding algorithm (SDA) based on radius constraint is presented. The proposed scheme preserves breadth-first searching nature, and the distinct radii for each decoding layer are theoretically derived from the system model with the noise statistics. In addition, based on the data range provided by the radius, a low complexity sorting strategy is proposed. The proposed method can apply to SDA with various path cost functions. Euclidean norm and sum of absolute difference are demonstrated in this paper. With SNR degradation less than 0.2dB, more than 47% and 90% computation complexity can be reduced in 16-QAM and 64-QAM 4 x 4 MIMO detection, respectively.
Generalized Globally-Coupled Low-Density Parity-Check Codes
(2018-01-01)
Liao, Yen-Chin
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Chang, Hsie-Chia
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Lin, Shu
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交大名義發表
;
National Chiao Tung University
In this paper, two globally-coupled low-density parity check (GC-LDPC) code constructing methods are presented. The first is a Reed-Solomon-like GC-LDPC code that eases the design parameter searching in algebraic code constructions. The parameters such as the finite field, the associated prime factors, or the number of local codes can be more easily determined. The directly masking approach, the second proposed scheme, facilitates flexible structure designs of the parity check matrices. The two approaches can be regarded as generalizations of the original GC-LDPC codes. The design examples and the simulation results show the feasibility of the proposed techniques. In addition to code constructions, some applications and usage scenarios of GC-LDPC codes are addressed as well.
Integrating Non-Repetitive LT Encoders With Modified Distribution to Achieve Unequal Erasure Protection
(2013-12-01)
Yen, Kuo-Kuang
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Liao, Yen-Chin
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Chen, Chih-Lung
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Zao, John K.
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Chang, Hsie-Chia
The performance of LT code is highly related to the code length. A decoder is more likely to deplete degree-1 encoding symbols and terminate during early stage when the code length is short. In this work, we modify the robust Soliton distribution (RSD) and increase the degree-1 proportion. More degree-1 encoding symbols can be generated to relieve early decoding termination. The proportion of low degrees, except for degree-1, is also reduced. Therefore, receivers collect less encoding symbols carrying redundant information. In addition, Non-Repetitive (NR) encoding scheme is proposed to avoid producing repeated degree-1 encoding symbols. To improve video transmission quality, previous studies redesign LT codes to provide Unequal Error Protection (UEP) for different Scalable Video Coding (SVC) layers. Unlike those studies to modify the code structure, we integrate multiple NR encoders to achieve UEP ability. Experimental results show that our UEP scheme outperforms previous studies in terms of the PSNR.
Low-complexity prediction techniques of K-best sphere decoding for MIMO systems
(2007)
Chang, Hsiu-Chi
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Liao, Yen-Chin
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Chang, Hsie-Chia
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In multiple-input multiple output (MIMO) systems, maximum likelihood (MEL) detection can provide good performance, however, exhaustively searching for the MEL solution becomes infeasible as the number of antenna and constellation points increases. Thus ML detection is often realized by K-best sphere decoding algorithm. In this paper, two techniques to reduce the complexity of K-best algorithm while remaining an error probability similar to that of the ML detection is proposed. By the proposed K-best with predicted candidates approach, the computation complexity can be reduced. Moreover, the proposed adaptive K-best algorithm provides a means to determine the value K according the received signals. The simulation result shows that the reduction in the complexity of 64-best algorithm ranges from 48% to 85%, whereas the corresponding SNR degradation is maintained within 0.13dB and 1.1dB for a 64-QAM 4 x 4 MIMO system.
Method and apparatus for carry estimation of reduced-width multipliers
(2008-07-03)
Liao, Yen-Chin
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Chang, Hsie-Chia
A low-error reduced-width multiplier is provided by the present invention. The multiplier can dynamically compensate the truncation error. The compensation value is derived by the dependencies among the multiplier partial products, and thus, can be analyzed according to the multiplication type and the multiplier input statistics.
METHOD AND APPARATUS FOR DECODING SHORTENED BCH CODES OR REED-SOLOMON CODES
(2009-10-15)
CHANG, Hsie-Chia
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Wu, Jau-Yet
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Liao, Yen-Chin
The present invention proposes a method and apparatus for decoding BCH codes and Reed-Solomon codes, in which a modified Berlekamp-Massey algorithm is used to perform the decoding process and the efficiency of the decoder can be improved by re-defining the error locating polynomial as a reverse error locating polynomial, while the operation of the decoding process can be further realized by a common re-configurable module. Furthermore, the architecture of the decoder is consisted of a plurality of sets of re-configurable modules in order to provide parallel operations with different degrees of parallel so that the decoding speed requirement of the decoder in different applications can be satisfied.
Method and apparatus for self-compensation on belief-propagation algorithm
(2007-12-06)
Liao, Yen-Chin
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Lin, Chien-Ching
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Chang, Hsie-Chia
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Liu, Chih-Wei
A self-compensation method includes: firstly using a min-sum algorithm to derive multiple output values in order to approach a operational result of the checking side of a belief-propagation; and then checking the present iteration number of decoding based on a checking rule; and finally, if in the previous step the present iteration number is identified with a to-be-corrected state, then performing a compensation procedure on the multiple output values, wherein the compensation term is dynamically selected in accordance with an input value of the checking nodes of the belief-propagation. The invention also provides an automatic compensation apparatus, which consists of devices such as a min-sum operating unit, and a dynamic quantization control unit, etc., which can be used, while executing the invented method described above, to decode the belief-propagation algorithm.
METHOD AND APPARATUS OF CANDIDATE LIST AUGMENTATION FOR CHANNEL CODING SYSTEM
(2010-02-04)
CHANG, Hsie-Chia
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Liao, Yen-Chin
The present invention discloses a candidate list augmentation apparatus with dynamic compensation in the coded MIMO systems. The proposed path augmentation technique in the present invention can expand the candidate paths derived from the detector to a distinct and larger list before computing the soft value of each bit. Consequently, the detector is allowed to deliver a smaller list, leading to reduction in computation complexity. Moreover, an additive correction term is introduced to dynamically compensate the approximation inaccuracy in the soft value generation, which improves the efficiency and performance of the coded MIMO systems.
Modified Robust Soliton Distribution (MRSD) with Improved Ripple Size for LT Codes
(2013-05-01)
Yen, Kuo-Kuang
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Liao, Yen-Chin
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Chen, Chih-Lung
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Chang, Hsie-Chia
;
電子工程學系及電子研究所
In this letter, we propose a scheme to modify robust Soliton distribution (RSD) with respect to the expected ripple size. We only adjust the proportion of degree 1, degree 2 and the maximum degree to derive the modified RSD (MRSD). Thus the proposed scheme contains only two variables and its complexity does not increase with the code length. Our objective is to increase the mean of the expected ripple size while decreasing its variance at the same time. Furthermore, sequential quadratic programming is introduced to maximize the objective function under certain constraints. Simulation results show that, with different code lengths, MRSD saves 2% to 5.8% overhead to decode entire input symbols, compared to RSD.
Non-Repetitive Encoding with Increased Degree-1 Encoding Symbols for LT Codes
(2012)
Yen, Kuo-Kuang
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Liao, Yen-Chin
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Chen, Chih-Lung
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Chang, Hsie-Chia
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電子工程學系及電子研究所
For LT codes with robust Soliton distribution, the ripple size is relatively small in the beginning of BP decoding process. Therefore, most of decoding termination occurs due to lack of ripple at early stage. In this study, we aim at reducing early decoding termination for low symbol loss probability. First, given k input symbols, the degree-1 proportion is increased to enlarge the average ripple size within the range 0 <= n <= k/2, where n is the number of decoded input symbols. Second, we propose Non-Repetitive (NR) encoding scheme to avoid generating repeated degree-1 encoding symbols. An NR encoder forces the first k degree-1 encoding symbols to connect to different input symbols. Simulation results show that NR encoding outperforms LT encoding in terms of symbol loss probability. Besides, less encoding symbols is needed to achieve high successful decoding probability when our scheme is applied. With k = 2000, NR encoding reaches a successful decoding probability of 99.6 % when overhead is 0.2, while LT encoding requires an overhead of 0.3 2 to reach the same probability.
OPERATING METHOD APPLIED TO LOW DENSITY PARITY CHECK (LDPC) DECODER AND CIRCUIT THEREOF
(2009-02-05)
LIU, Chih-Hao
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Liao, Yen-Chin
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Lee, Chen-Yi
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Chang, Hsie-Chia
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Hsu, Yarsun
An operating method applied to low density parity check (LDPC) decoders and the circuit thereof are proposed, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the different between the newly generated check messages and the previously check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. In the other way, the required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.
Scalable Globally-Coupled Low-Density Parity Check Codes
(2018-01-01)
Liao, Yen-Chin
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Chang, Hsie-Chia
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Lin, Shu
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交大名義發表
;
National Chiao Tung University
This paper presents a technique to scale up an LDPC code to any desired block length. Under certain constraints, the scaled LDPC code results in a special case of globally-coupled-LDPC code. The proposed scheme can construct globally-coupled-LDPC codes from any short LDPC codes. A design example targeting for NAND flash memory applications is addressed and simulated. The results show the feasibility of constructing a structural long LDPC code by scaling from a short code.