Browsing by Author "Liao Yen-Chin"

Now showing 1 - 5 of 5

Method and apparatus for decoding shortened BCH codes or reed-solomon codes
(2011-05-10)
Chang Hsie-Chia
;
Wu Jau-Yet
;
Liao Yen-Chin
The present invention proposes a method and apparatus for decoding BCH codes and Reed-Solomon codes, in which a modified Berlekamp-Massey algorithm is used to perform the decoding process and the efficiency of the decoder can be improved by re-defining the error locating polynomial as a reverse error locating polynomial, while the operation of the decoding process can be further realized by a common re-configurable module. Furthermore, the architecture of the decoder is consisted of a plurality of sets of re-configurable modules in order to provide parallel operations with different degrees of parallel so that the decoding speed requirement of the decoder in different applications can be satisfied.
Method and apparatus of candidate list augmentation for channel coding system
(2012-08-28)
Chang Hsie-Chia
;
Liao Yen-Chin
The present invention discloses a candidate list augmentation apparatus with dynamic compensation in the coded MIMO systems. The proposed path augmentation technique in the present invention can expand the candidate paths derived from the detector to a distinct and larger list before computing the soft value of each bit. Consequently, the detector is allowed to deliver a smaller list, leading to reduction in computation complexity. Moreover, an additive correction term is introduced to dynamically compensate the approximation inaccuracy in the soft value generation, which improves the efficiency and performance of the coded MIMO systems.
Method for carry estimation of reduced-width multipliers
(2014-01-28)
Liao Yen-Chin
;
Chang Hsie-Chia
A low-error reduced-width multiplier is provided by the present invention. The multiplier can dynamically compensate the truncation error. The compensation value is derived by the dependencies among the multiplier partial products, and thus, can be analyzed according to the multiplication type and the multiplier input statistics.
Method for carry estimation of reduced-width multipliers
(2011-07-28)
Liao Yen-Chin
;
Chang Hsie-Chia
A low-error reduced-width multiplier is provided by the present invention. The multiplier can dynamically compensate the truncation error. The compensation value is derived by the dependencies among the multiplier partial products, and thus, can be analyzed according to the multiplication type and the multiplier input statistics.
Operating method and circuit for low density parity check (LDPC) decoder
(2012-01-31)
Liu Chih-Hao
;
Liao Yen-Chin
;
Lee Chen-Yi
;
Chang Hsie-Chia
;
Hsu Yarsun
An operating method and a circuit for low density parity check (LDPC) decoders, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the difference between the newly generated check messages and the previous check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. The required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.