Browsing by Author "Lien, C. H."

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A new series resistance and mobility extraction method by BSIM model for nano-scale MOSFETs
(2006)
Chen, William P. N.
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Su, P.
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Wang, J. S.
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Lien, C. H.
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Chang, C. H.
Highly Scalable Hafnium Oxide Memory with Improvements of Resistive Distribution and Read Disturb Immunity
(2009)
Chen, Y. S.
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Lee, H. Y.
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Chen, P. S.
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Gu, P. Y.
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Chen, C. W.
A 30x30 nm(2) HfOx resistance random access memory (RRAM) with excellent electrical performances is demonstrated for the scaling feasibility in this work. A 1 Kb one transistor and one resistor (1T1R) array with robust characteristics was also fabricated successfully. The device yield of the 1 Kb array is 100%, and the endurance for these devices can exceed 10(6) cycles by a pulse width of 40 ns. Two effective verification methods, which make a tight distribution of high resistance (R-HIGH) and low resistance (R-LOW) are proposed for the array to ensure a good operation window. A thin A1O(x) buffer layer under the HfOx layer was adopted to enhance the read disturb immunity. Without large parasitic capacitance, the 1T1R RRAM devices exhibit excellent program(PGM)/erase(ERS) disturb immunity.
PD-SOI MOSFET Body-to-Body Leakage Scaling Trend and Optimization
(2008)
Lo, H. C.
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Luo, W. C.
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Lu, W. Y.
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Cheng, C. F.
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Wu, Benny
Body-to-Body leakage (BBL) in stacked transistor configuration has been characterized by different back gate biases (Vbg), SOI thicknesses, and poly spacings. BBL increases significantly from 65nm to 45nm node mainly due to smaller poly spacing and shallower S/D junctions. By implant optimization and reduction of the SOI thickness, BBL can be reduced below reverse junction leakage level.
The Characteristics and Control of Body-to-Body Leakage Current in PD-SOI
(2009)
Lo, H. C.
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Luo, W. C.
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Lu, W. Y.
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Cheng, C. F.
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Chen, T. L.
Body-to-body leakage (BBL) current in a partially depleted silicon-on-insulator (PD-SOI) device is increased significantly as polyspacing (PS) is reduced in technology scaling. We found out that the BBL has a great impact to Vt variation. We have demonstrated that the BBL can be minimized drastically by implant optimization. The dependence of the BBL on silicon film thickness, e-SiGe structure, and dopant diffusivity is also discussed in this paper. The layout effect of the BBL current in PD-SOI devices has been characterized with different PSs, device widths, and polylengths. Finally, we have demonstrated that the BBL current can be reduced below junction leakage level. (C) 2009 The Electrochemical Society. [DOI:10.1149/1.3223971] All rights reserved.