Browsing by Author "Lien, Chen-Hsin"

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A novel nanowire channel poly-Si TFT functioning as transistor and nonvolatile SONOS memory
(2007-09-01)
Chen, Shih-Ching
;
Chang, Ting-Chang
;
Liu, Po-Tsun
;
Wu, Yung-Chun
;
Lin, Po-Shun
In this letter, a polycrystalline silicon thin-film transistor consisting of silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire (NW) channels was investigated for the applications of transistor and nonvolatile memory. The proposed device, which is named as NW SONOS-TFT, has superior electrical characteristics of transistor, including a higher drain current, a smaller threshold voltage (V-th), and a steeper subthreshold slope. Moreover, the NW SONOS-TFT also can exhibit high program/erase efficiency under adequate bias operation. The duality of both transistor and memory device for the NW SONOS-TFT can be attributed to the trigate structure and channel corner effect.
Analog Circuit Applications Based on All-2D Ambipolar ReSe2 Field-Effect Transistors
(2019-05-01)
Lee, Ko-Chun
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Yang, Shih-Hsien
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Sung, Yung-Shang
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Chang, Yuan-Ming
;
Lin, Che-Yi
Complementary circuits based on 2D materials show great promise for next-generation electronics. An ambipolar all-2D ReSe2 field-effect transistor (FET) with a hexagonal boron nitride gate dielectric is fabricated and its electronic characteristics are comprehensively studied by temperature dependence and noise measurements. Ambipolar transfer characteristics are achieved owing to the tunable Fermi level of the graphene contact and negligible and 30 meV Schottky barrier heights for the n- and p-channel regimes, respectively. An inverter is also fabricated to demonstrate ambipolar ReSe2 FET operation in a logic circuit. Furthermore, a p/n switchable unipolar FET is designed and shows potential for building complimentary circuits from a signal device. This work demonstrates the potential of all-2D ReSe2 FETs and makes available new approaches for designing next-generation devices.
Atomically thin van der Waals tunnel field-effect transistors and its potential for applications
(2019-03-08)
Yang, Shih-Hsien
;
Yao, You-Teng
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Xu, Yong
;
Lin, Che-Yi
;
Chang, Yuan-Ming
Power dissipation is a crucial problem as the packing density of transistors increases in modern integrated circuits. Tunnel field-effect transistors (TFETs), which have high energy filtering provided by band-to-band tunneling (BTBT), have been proposed as an alternative electronics architecture to decrease the energy loss in bias operation and to achieve steep switching at room temperature. Very recently, the BTBT behavior has been demonstrated in van der Waals heterostructures by using unintentionally doped semiconductors. The reason of the BTBT formation is attributed to a significant band bending near the heterointerface, resulting in carrier accumulations. In this work, to investigate charge transport in type-III transistors, we adopted the same band-bending concept to fabricate van der Waals BP/MoS2 heterostructures. Through analyzing the temperature dependence of their electrical properties, we carefully ruled out the contribution of metal-semiconductor contact resistances and improved our understanding of carrier injection in 2D type-III transistors. The BP/MoS2 heterostructures showed both negative differential resistance and 1/f(2) current fluctuations, strongly demonstrating the BTBT operation. Finally, we also designed a TFET based on this heterostructure with an ionic liquid gate, and this TFET demonstrated an subthreshold slope can successfully surmount the thermal limit of 60 mV/decade. This work improves our understanding of charge transport in such layered heterostructures and helps to improve the energy efficiency of next-generation nanoscale electronics.
Characteristics of poly-Si TFT combined with nonvolatile SONOS memory and nanowire channels structure
(2007-12-15)
Chen, Shih-Ching
;
Chang, Ting-Chang
;
Liu, Po-Tsun
;
Wu, Yung-Chun
;
Lin, Po-Shun
In this work, we study a polycrystalline silicon thin-film transistor (poly-Si TFT) combined with a silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire channels structure for the applications of transistor and nonvolatile memory. The proposed device named with NW SONOS-TFT has superior electrical characteristics of transistor and also can exhibit high program/erase (P/E) efficiency under adequate bias operation. The V-th decreases from 2.45 V to 1.76 V and subthreshold swing reduces from 0.57 V/decade to 0.42 V/decade. The programming V-th shift is improved from 2.2 V to 3.3 V at 14 V for 1 s and the erasing V-th shift is improved from -0.3 V to -1.3 V at -14 V for 1 s. The dramatic improvement can be attributed to the tri-gate structure and corner effect. In addition, the memory device has a promising data retention behavior at 85 degrees C and a 0.8 V memory window after 5 x 10(3) P/E cycles operations. Hence, the NW SONOS-TFT is suitable for application in the future system-on-panel display. (C) 2007 Elsevier B.V. All rights reserved.
Fast-IV Measurement Investigation of the Role of TiN Gate Nitrogen Concentration on Bulk Traps in HfO2 Layer in p-MOSFETs
(2017-06-01)
Lu, Ying-Hsin
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Chang, Ting-Chang
;
Liao, Jih-Chien
;
Chen, Li-Hui
;
Lin, Yu-Shan
This letter investigates the role of the TiN gate's nitrogen concentration on bulk traps in the HfO2 layer in p-MOSFETs using fast I-V measurement. During negative bias temperature instability, the holes trapped in the HfO2 layer will induce Vth degradation. The fast I-V double sweep confirms the holes are trapped in process-related pre-existing defects. These defects are interstitial-type, influenced by the nitrogen in the TiN gate diffusing to the HfO2 layer when the device undergoes thermal annealing. Moreover, these nitrogen interstitials increase with increasing TiN gate nitrogen concentration, which induces more holes being trapped in the HfO2 layer.
High Mobilities in Layered InSe Transistors with Indium-Encapsulation-Induced Surface Charge Doping
(2018-11-02)
Li, Mengjiao
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Lin, Che-Yi
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Yang, Shih-Hsien
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Chang, Yuan-Ming
;
Chang, Jen-Kuei
Tunability and stability in the electrical properties of 2D semiconductors pave the way for their practical applications in logic devices. A robust layered indium selenide (InSe) field-effect transistor (FET) with superior controlled stability is demonstrated by depositing an indium (In) doping layer. The optimized InSe FETs deliver an unprecedented high electron mobility up to 3700 cm(2) V-1 s(-1) at room temperature, which can be retained with 60% after 1 month. Further insight into the evolution of the position of the Fermi level and the microscopic device structure with different In thicknesses demonstrates an enhanced electron-doping behavior at the In/InSe interface. Furthermore, the contact resistance is also improved through the In insertion between InSe and Au electrodes, which coincides with the analysis of the low-frequency noise. The carrier fluctuation is attributed to the dominance of the phonon scattering events, which agrees with the observation of the temperature-dependent mobility. Finally, the flexible functionalities of the logic-circuit applications, for instance, inverter and not-and (NAND)/not-or (NOR) gates, are determined with these surface-doping InSe FETs, which establish a paradigm for 2D-based materials to overcome the bottleneck in the development of electronic devices.
High-performance polycrystalline silicon thin-film transistors with oxidenitride-oxide gate dielectric and multiple nanowire channels
(2006-11-25)
Chen, Shih-Ching
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Chang, Ting-Chang
;
Liu, Po-Tsun
;
Wu, Y. C.
;
Tsai, C. C.
This work presents a method to enhance the performance of polycrystalline silicon thin film transistors (poly-Si TFTs) by using an oxide-nitride-oxide (ONO) gate dielectric and the multiple nanowire channels structure. Experimental results indicate that the performance of the device was enhanced by using the ONO multilayer, because the ONO gate dielectric constant is increased compared to the conventional oxide gate dielectric. Additionally, the TFTs with a ten nanowire channel structure (NW-TFTs) have superior electrical characteristics compared to other TFTs. This is because a structure with more corners and a shorter radius has better gate control due to the corner effect. (c) 2006 Elsevier B.V. All rights reserved.
Impact of electrode thermal conductivity on high resistance state level in HfO2-based RRAM
(2020-09-23)
Lin, Shih-Kai
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Wu, Cheng-Hsien
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Chen, Min-Chen
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Chang, Ting-Chang
;
Lien, Chen-Hsin
This study examines the influence of different electrode thermal conductivity on switching behavior during the reset process. Electrical analysis methods and an analysis of current conduction mechanism indicate that better thermal conductivity in the electrode will require larger input power in order to induce more active oxygen ions to take part in the reset process. More active oxygen ions result in a more oxidized switching layer, and cause the effective switching gap (d(sw)) to become larger in the reset process. The effect of the electrode thermal conductivity and input power are explained by our model and clarified by electrical analysis methods.
Low-Voltage Operational, Low-Power Consuming, and High Sensitive Tactile Switch Based on 2D Layered InSe Tribotronics
(2019-05-09)
Li, Mengjiao
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Yang, Feng-Shou
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Hsiao, Yung-Chi
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Lin, Che-Yi
;
Wu, Hsing-Mei
Electronics based on layered indium selenide (InSe) channels exhibit promising carrier mobility and switching characteristics. Here, an InSe tribotronic transistor (denoted as w/In InSe T-FET) obtained through the vertical combination of an In-doped InSe transistor and triboelectric nanogenerator is demonstrated. The w/In InSe T-FET can be operated by adjusting the distance between two triboelectrification layers, which generates a negative electrostatic potential that serves as a gate voltage to tune the charge carrier transport behavior of the InSe channel. Benefiting from the surface charging doping of the In layer, the w/In InSe T-FET exhibits high reliability and sensitivity with a large on/off current modulation of 10(6) under a low drain-source voltage of 0.1 V and external frictional force. To demonstrate its function as a power-saving tactile sensor, the w/In InSe T-FET is used to sense INSE in Morse code and power on a light-emitting diode. This work reveals the promise of 2D material-based tribotronics for use in nanosensors with low power consumption as well as in intelligent systems.
Multifunctional full-visible-spectrum optoelectronics based on a van der Waals heterostructure
(2019-12-01)
Yang, Shih-Hsien
;
Lee, Ko-Chun
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Tsai, Meng-Yu
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Chang, Yuan-Ming
;
Lin, Che-Yi
Multifunctional devices are expected to allow development of low-cost, highly integrated, and energy-efficient electronics for the internet of things (IoT) era. Here, we demonstrate an all-two-dimensional ReSe2/h-BN/graphene heterostructure (ReSe2 HS) consisting of a vertically coupled ReSe2 field-effect transistor and charge storage component, which possesses multifunctional characteristics for use in electronics and optoelectronics. As an electrically controlled non-volatile memory (NVM), the ReSe2 HS delivers high-performance multilevel data storage with a readout on/off current ratio exceeding 10(5) and excellent durability (> 10(4) s) at an ultralow V-ds of 50 mV, which benefits to the development of power saving devices. The ReSe2 HS design and high-photoresponsivity ReSe2 channel also achieve an energy efficient optical NVM with full-visible-spectrum distinction. Besides, the ReSe2 HS displays unique ambipolarity to operate as either an inverter or frequency doubler. We further propose a power-free ReSe2 HS optical memory matrix to simplify imaging systems. The ReSe2 HS shows promise for use in light-programmable information storage systems and neuromorphic computation with low power consumption.
Nonvolatile polycrystalline silicon thin-film-transistor memory with oxide/nitride/oxide stack gate dielectrics and nanowire channels
(2007-03-19)
Chen, Shih-Ching
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Chang, Ting-Chang
;
Liu, Po-Tsun
;
Wu, Yung-Chun
;
Yeh, Ping-Hung
In this work, the authors study a polycrystalline silicon thin-film transistor (poly-Si TFT) with oxide/nitride/oxide (ONO) stack gate dielectrics and multiple nanowire channels for the applications of both nonvolatile silicon-oxide-nitride-oxide-silicon (SONOS) memory and switch transistor. The proposed device named as nanowire SONOS-TFT has superior electrical characteristics of a transistor such as on/off current ratio, threshold voltage (V-th), and subthreshold slope due to the good gate control ability originated from fringing electrical field effects. Moreover, the proposed device under adequate operation scheme can exhibit high program/erase efficiency and good retention time characteristics at high temperature. (c) 2007 American Institute of Physics.
Nonvolatile Si/SiO2/SiN/SiO2/Si type polycrystalline silicon thin-film-transistor memory with nanowire channels for improvement of erasing characteristics
(2007-11-05)
Chen, Shih-Ching
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Chang, Ting-Chang
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Liu, Po-Tsun
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Wu, Yung-Chun
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Chin, Jing-Yi
A silicon-oxide-nitride-oxide-silicon type polycrystalline silicon thin-film transistor (poly-Si TFT) with nanowire channels was investigated for both transistor and memory applications. The poly-Si TFT memory device has superior electrical characteristics, such as higher drain current, smaller threshold voltage, and steeper subthreshold slope. Also, the simulation result on electrical field reveals that the electrical field across the tunnel oxide is enhanced and that across the blocking oxide is reduced at the corner regions. This will lead to the parasitic gate injection activity and the erasing speed can be apparently improved in the memory device due to the pronounced corner effect and narrow channel width.
Oxidation-boosted charge trapping in ultra-sensitive van der Waals materials for artificial synaptic features
(2020-06-12)
Yang, Feng-Shou
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Li, Mengjiao
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Lee, Mu-Pai
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Ho, I-Ying
;
Chen, Jiann-Yeu
Exploitation of the oxidation behaviour in an environmentally sensitive semiconductor is significant to modulate its electronic properties and develop unique applications. Here, we demonstrate a native oxidation-inspired InSe field-effect transistor as an artificial synapse in device level that benefits from the boosted charge trapping under ambient conditions. A thin InOx layer is confirmed under the InSe channel, which can serve as an effective charge trapping layer for information storage. The dynamic characteristic measurement is further performed to reveal the corresponding uniform charge trapping and releasing process, which coincides with its surface-effect-governed carrier fluctuations. As a result, the oxide-decorated InSe device exhibits nonvolatile memory characteristics with flexible programming/erasing operations. Furthermore, an InSe-based artificial synapse is implemented to emulate the essential synaptic functions. The pattern recognition capability of the designed artificial neural network is believed to provide an excellent paradigm for ultra-sensitive van der Waals materials to develop electric-modulated neuromorphic computation architectures. Developing efficient memory and artificial synaptic systems based on environmentally sensitive van der Waals materials remains a challenge. Here, the authors present a native oxidation-inspired InSe field-effect transistor that benefits from a boosted charge trapping behavior under ambient conditions.
Oxygen-Sensitive Layered MoTe2 Channels for Environmental Detection
(2019-12-18)
Yang, Shih-Hsien
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Lin, Che-Yi
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Chang, Yuan-Ming
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Li, Mengjiao
;
Lee, Ko-Chun
The oxygen (O-2)-dependent resistance change of multilayered molybdenum ditelluride (MoTe2) channels was characterized. A variation of the channel resistance could reproducibly determine relative O-2 content (denoted as the O-2 index). We found that Joule heating in a layered MoTe2 field-effect transistor caused the O-2 index to decrease drastically from 100 to 12.1% in back gate modulation. Furthermore, Joule heating caused effective O-2 desorption from the MoTe2 surface and repeatable O-2 detection by multilayered MoTe2 channels was realized. This work not only explored the influence of O-2 on the electrical properties of multilayered MoTe2 channels but also revealed that MoTe2 channels are promising for sensing O-2 in an environmental condition.
Pi-shape gate polycrystalline silicon thin-film transistor for nonvolatile memory applications
(2007-11-19)
Chen, Shih-Ching
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Chang, Ting-Chang
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Liu, Po-Tsun
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Wu, Yung-Chun
;
Ko, Chin-Cheng
In this work, we studied a pi-shape gate polycrystalline silicon thin-film transistor (poly-Si TFT) with silicon-oxide-nitride-oxide-silicon (SONOS) layers and nanowire channels for the application of electric driver and nonvolatile memory. The proposed pi-gate TFT-SONOS has superior transfer characteristics and its output characteristic also exhibits the high driving current and the suppression of the kink effect. For memory application, the device can provide high program/erase efficiency and large threshold voltage shift under adequate bias operation. The enhanced performance for the pi-gate TFT-SONOS is attributed to the larger effective channel width and the number of channel corners. (C) American Institute of Physics.
Reversible and Precisely Controllable p/n-Type Doping of MoTe2 Transistors through Electrothermal Doping
(2018-03-27)
Chang, Yuan-Ming
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Yang, Shih-Hsien
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Lin, Che-Yi
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Chen, Chang-Hung
;
Lien, Chen-Hsin
Precisely controllable and reversible p/n-type electronic doping of molybdenum ditelluride (MoTe2) transistors is achieved by electrothermal doping (E-doping) processes. E-doping includes electrothermal annealing induced by an electric field in a vacuum chamber, which results in electron (n-type) doping and exposure to air, which induces hole (p-type) doping. The doping arises from the interaction between oxygen molecules or water vapor and defects of tellurium at the MoTe2 surface, and allows the accurate manipulation of p/n-type electrical doping of MoTe2 transistors. Because no dopant or special gas is used in the E-doping processes of MoTe2, E-doping is a simple and efficient method. Moreover, through exact manipulation of p/n-type doping of MoTe2 transistors, quasi-complementary metal oxide semiconductor adaptive logic circuits, such as an inverter, not or gate, and not and gate, are successfully fabricated. The simple method, E-doping, adopted in obtaining p/n-type doping of MoTe2 transistors undoubtedly has provided an approach to create the electronic devices with desired performance.
Room-Temperature Ferroelectricity in Hexagonally Layered alpha-In2Se3 Nanoflakes down to the Monolayer Limit
(2018-12-12)
Xue, Fei
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Hu, Weijin
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Lee, Ko-Chun
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Lu, Li-Syuan
;
Zhang, Junwei
2D ferroelectric material has emerged as an attractive building block for high density data storage nanodevices. Although monolayer van der Waals ferroelectrics have been theoretically predicted, a key experimental breakthrough for such calculations is still not realized. Here, hexagonally stacking alpha-In2Se3 nanoflake, a rarely studied van der Waals polymorph, is reported to exhibit out-of-plane (OOP) and in-plane (IP) ferroelectricity at room temperature. Ferroelectric multidomain states in a hexagonal alpha-In2Se3 nanoflake with uniform thickness can survive to 6 nm. Most strikingly, the electric-field-induced polarization switching and hysteresis loop are, respectively, observed down to the bilayer and monolayer (approximate to 1.2 nm) thicknesses, which designates it as the thinnest layered ferroelectric and verifies the corresponding theoretical calculation. In addition, two types of ferroelectric nanodevices employing the OOP and IP polarizations in 2H alpha-In2Se3 are developed, which are applicable for nonvolatile memories and heterostructure-based nanoelectronics/optoelectronics.
The Effect of Humidity on Reducing Forming Voltage in Conductive-Bridge Random Access Memory With an Alloy Electrode
(2019-10-01)
Lin, Shih-Kai
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Chen, Min-Chen
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Chang, Ting-Chang
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Lien, Chen-Hsin
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Chang, Jing-Shuen
This letter investigates Au30Ag70 (alloy electrode)/SiO2/TiN conductive-bridge random access memory (CBRAM) to verify the influence of ambient conditions on forming voltage (V-F) and the location of galvanic reaction. Previous literature demonstrates that the galvanic reaction in CBRAM with an alloy electrode results in a lower V-F. In this work, a higher environmental H2O concentration results in a decrease in V-F. From this change in VF, we infer that environmental H2O concentration influences the amount of galvanic reaction. Moreover, we verify the location of the galvanic reaction by varying electrode thickness. Finally, we propose a physical model to explain our observations.