Browsing by Author "Lin, CC"

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A 3.33Gb/s (1200,720) low-density parity check code decoder
(2005)
Lin, CC
;
Lin, KL
;
Chang, HC
;
Lee, CY
;
電子工程學系及電子研究所
In this paper, a (1200,720) LDPC decoder based on an irregular parity check matrix is presented. For achieving higher chip density and less critical path delay, the proposed architecture features a new data reordering such that only one specific data bus exists between message memories and computational units. Moreover, the LDPC decoder can also process two different codewords concurrently to increase throughput and datapath efficiency. After chip implementation, a 3.33Gb/s data rate is achieved with 8 decoding iterations in the 21.23mm(2) 0.18 mu m silicon area. The other 0.13 mu m chip with the 10.24mm(2) core can further reach a 5.92Gb/s data rate under 1.02V supply.
A COMM baseband processor with robust synchronization for high-speed WLAN applications
(2004)
Liu, HY
;
Yu, YH
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Lin, CC
;
Chung, CC
;
Hsu, TY
in this paper, a high-performance and low-cost COFDM baseband processor is presented. With algorithm exploration in channel estimation and phase error tracking, synchronization becomes more robust to enhance system performance. And better design SNR (1.35similar to7.16 dB) can be achieved compared to current solutions. Moreover through architectural exploration, the proposed baseband processor designed in 0.18 um CMOS process contains only 370 K logic gates and 3.3 K byte memory. Measurement results show that better hardware efficiency and performance enhancement is achieved for high-speed WLAN applications.
A dual mode channel decoder for 3GPP2 mobile wireless communications
(2004)
Lin, CC
;
Shih, YH
;
Chang, HC
;
Lee, CY
;
電子工程學系及電子研究所
This paper presents a turbo and Viterbi decoder single chip for 3GPP2 standard. The turbo decoding with a maximum block length of 20,730 and Viterbi decoding with various coding rates are implemented to provide maximum 4.52Mb/s and 5.26Mb/s data rates respectively The memory access is reduced by the input caching scheme. And the system complexion is lowered by the efficient interleaver design. This chip is fabricated in a 0.18mum six-metal standard CMOS process, and the measured power dissipation is 83mW while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block.
A dual-beam micro-CPW leaky-mode antenna
(2000-02-01)
Lin, CC
;
Tzuang, CKC
;
電信工程研究所
;
Institute of Communications Engineering
Quasi-planar leaky-mode antenna employing the second higher order leaky mode of even symmetry in its leaky-wave regime has been proposed for a new antenna configuration consisting of a microstrip and a coplanar waveguide (CPW) on both sides of the substrate. The new antenna, also known as the micro-CPW antenna, is directly fed by a CPW line without matching circuit. One particular K-band antenna of 36 mm long [about 2.7 free-space wavelengths (lambda(0)) at 22.1 GHz] shows 5.3% impedance bandwidth for VSWR's less than 2.0 for frequencies between 21.927-23.110 GHz, 11.0-dB antenna gain, and 90.02% efficiency. Detailed analyses show that the dual-beam antenna is linearly polarized along two slanted lines, which lie in the longer axes of the ellipses that approximate the radiation contours. Both theoretical and experimental data for the micro-CPW antenna agree very well for the particular design. The proposed micro-CPW antenna is suitable for active integrated antenna integration at higher microwave and millimeter-wave frequencies.
A dynamic normalization technique for decoding LDPC codes
(2005)
Liao, YC
;
Lin, CC
;
Liu, CW
;
Chang, HC
;
電子工程學系及電子研究所
In this paper, a dynamic normalization technique is proposed to approximate the nonlinear operation in decoding LDPC codes. The criterion in determining the normalization factor is also presented with theoretical analysis. The proposed method improves the approximation accuracy as well as the error performance of min-sum algorithm. Furthermore, the hardware implementation benefits from a simplified normalization scheme, leading to reductions in complexity and implementation loss.
A low power and high speed viterbi decoder chip for WLAN applications
(2003)
Lin, CC
;
Wu, CC
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a 166Mb/s, 64-state, radix-4, 16-level soft decison Viterbi decoder for high speed WLAN applications. With the path merging and trace forward techniques, the memory read operations are reduced to save power cunsumption. A test chip is fabricated in 0.35 mum 1P4M CMOS process, and can achieve the maximum throughout rate of 166Mbit/s under 3.3V The measured power consumption is below 55mW under 66M6/s throughput rate at 2.2V.
A low power turbo/Viterbi decoder for 3GPP2 applications
(2006-04-01)
Lin, CC
;
Shih, YH
;
Chang, HC
;
Lee, CY
;
電子工程學系及電子研究所
This paper presents a channel decoder that completes both turbo and Viterbi decodings, which are pervasive in many wireless communication systems, especially those that require very low signal-to-noise ratios. The trellis decoding algorithm merges them with less redundancy. However, the implementation is still challenging due to the power consumption in wearable devices. This research investigates an optimized memory scheme and rescheduled data flow to reduce power consumption and chip area. The memory access is reduced by buffering the input symbols, and the area is reduced by reducing the embedded interleaver memory. A test chip is fabricated in a 1.8 V 0.18-mu m standard CMOS technology and verified to provide 4.25-Mb/s turbo decoding and 5.26-Mb/s Viterbi decoding. The measured power dissipation is 83 mW, while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block. The power consumption in Viterbi decoding is 25.1 mW in the 1-Mb/s data rate. The measurement shows the power dissipation is 83 mW for the turbo decoding with six iterations at 3.1 Mb/s, and 25.1 mW for the Viterbi decoding at 1 Mb/s.
A low-complexity B-spline based digital sample rate conversion circuit architecture
(2005)
Lin, CC
;
Chi, HF
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電信工程研究所
;
Institute of Communications Engineering
This paper presents a low-complexity digital sample rate conversion (SRC) circuit architecture with arbitrary factor conversion ratio. The strategy in deciding SRC system parameters is given to guarantee that both the anti-imaging and the anti-aliasing requirements can be satisfied. The significant reduction in the complexity of the proposed structure allows simple VLSI implementation without affecting the performance. A parallel cascaded integrator comb (CIC) filter circuit without high intermediate sample rate and a multiplier-less linear interpolator are also developed to obtain a cost-effective and high-speed SRC circuit.
A low-power Reed-Solomon decoder for STM-16 optical communications
(2002)
Chang, HC
;
Lin, CC
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a low-power Reed-Solomon (RS) decoder for STM-16 optical communications is presented. It mainly contains one (255,239) RS decoder and four 2K-bit embedded memory for correcting the received codewords. Except the novel syndrome calculator reducing half the syndrome computations, our proposal also features a modified Berlekamp-Massey algorithm in the key equation solver and a terminated mechanism in the Chien search circuit. The (255,239) RS decoder is implemented by 0.25mum CMOS 1P5M standard cells with gate counts of 32.9K and area of 2.03 mm(2). Simulation results show our approach can work successfully at the data rate of 2.5-Gbps and achieve 80% reduction of power dissipation on the average.
A new channel equalizer for OFDM-based wireless communications
(2005)
Chang, YM
;
Kuang, CW
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Lin, CC
;
Sang, TS
;
Chang, HC
This paper presents a new channel equalizer for OFDM-based communication systems. The channel equalizer consists of the adaptive estimation of channel frequency response (CFR) and the signal recovery. CFR is obtained by the two-dimensional linear interpolation of pilots from the frequency axis and the time axis. To avoid the noise enhancement in signal recovery, maximum-likelihood sequence estimation (MLSE) is applied to improve 1.5dB in SNR while using Rayleigh fading channel model with 30Hz Doppler frequency shift. As compared to the linear equalizer without feedback, the division free approach provides more accurate signal recovery in circuit implementation.
A note on computing the saddle values in isosurface polygonization
(1997)
Lin, CC
;
Ching, YT
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資訊工程學系
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Department of Computer Science
The ambiguity problem of the marching cubes method can be solved by constructing isosurfaces that are topologically consistent with the trilinear interpolant. This can be achieved by computing the saddle values of the interpolant. In this note, we analyze the trilinear interpolant and derive an efficient method of computing the saddle values.
A novel potential-based path planning of 3-D articulated robots with moving bases
(2004-07-01)
Lin, CC
;
Pan, CC
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Chuang, JH
;
資訊工程學系
;
Department of Computer Science
This paper proposes a novel path planning algorithm of 3-D articulated robots with moving bases based on a generalized potential field model. The approach computes, similar to that done in electrostatics, repulsive forces and torques between charged objects. A collision-free path can be obtained by locally adjusting the robot configuration to search for minimum potential configurations using these forces and torques. The proposed approach is efficient since these potential gradients are analytically tractable. In order to speedup the computation, a sequential planning strategy is adopted. Simulation results show that the proposed algorithm works well, in terms of collision avoidance and computation efficiency.
A novel potential-based path planning of 3-D articulated robots with moving bases
(2003)
Lin, CC
;
Pan, CC
;
Chuang, JH
;
資訊工程學系
;
Department of Computer Science
This paper proposes a novel path planning algorithm of 3-D articulated robots with moving bases based on a generalized potential field model. The approach computes, similar to that done in electrostatics, repulsive force and torque between charged objects. A collision-free path can be obtained by locally adjusting the robot configuration to search for minimum potential configurations using these force and torque. The proposed approach is efficient since these potential gradients are analytically tractable. In order to speedup the computation, a sequential planning strategy is adopted. Simulation results show that the proposed algorithm works well, in terms of collision avoidance and computation efficiency.
A potential-based generalized cylinder representation
(2004-12-01)
Chuang, JH
;
Ahuja, N
;
Lin, CC
;
Tsai, CH
;
Chen, CH
Generalized cylinder (GC) is a class of parametric shapes that is very flexible and capable of modeling many different types of real-world objects, and have subsequently been the focus of considerable research in the vision community. Most of the related works proposed previously have dealt with the recovery of 3D shape description of objects based on the GC representation from one or more 2D image data. Different from the objective of the previous works, in this paper, we will propose a new approach to obtain a GC-based shape description of 3D objects. The proposed approach of deriving the GC axis is a further extension of the potential-based skeletonization approach presented in (IEEE Trans. Pattern Anal. Mach. Intell. 22(11) (2000) 1241). Simulation results demonstrate that the derived GC representation will yield better approximation of object shape than that based on simpler subclasses of GC since there is, in principle, no restriction on the topology of the GC axis and the shape of the cross-sections. (C) 2004 Elsevier Ltd. All rights reserved.
A potential-based path planning of articulated robots with 2-DOF joints
(2005)
Chuang, JH
;
Lin, CC
;
Kao, JH
;
Hsieh, CT
;
資訊工程學系
This paper proposes a potential-based path planning algorithm of articulated robots with 2-DOF joints. The algorithm is an extension of a previous algorithm developed for 3-DOF joints. While 3-DOF joints result in a very straightforward potential minimization algorithm, 2-DOF joints are obviously more practical for active operations. The proposed approach computes repulsive force and torque between charged objects by using generalized potential model. A collision-free path can be obtained by locally adjusting the robot configuration to search for minimum potential configurations using these force and torque. The optimization of path safeness, through the innovative potential minimization algorithm, makes the proposed approach unique. In order to speedup the computation, a sequential planning strategy is adopted. Simulation results show that the proposed algorithm works well compared with the algorithm for 3-DOF joints, in terms of collision avoidance and computation efficiency.
A power and area efficient multi-mode FEC processor
(2004)
Tseng, YC
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Lin, CC
;
Chang, HC
;
Lee, CY
;
電子工程學系及電子研究所
Forward Error Correction (FEC) is a key component in communication system which mostly contains scrambler, Reed-Solomon coding, interleaving, and trellis coding. For the performance and complexity issues, design parameters are different in various applications. In this paper, a multi-mode FEC processor is presented to meet different system requirements with a power and area efficient architecture. The proposed processor is fully compliant to ITU-T J.83 cable modem system including the reconfigurable Reed-Solomon decoder and memory-based universal convolutional interleaver. With 0.18um 1P6M CMOS technology, the simulation result shows the FEC decoder can work over 100MHz while costs 54.5K gate counts and two 376x8 bits embedded duel-port SRAM. The average power consumption in most critical mode is about 34.2mW at 100MHz. While running at 7MHz that meets symbol rate of cable modem, the power dissipation is 2.32mW.
A practical routing protocol for vehicle-formed mobile ad hoc networks on the roads
(2005)
Wang, SY
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Lin, CC
;
Hwang, YW
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Tao, KC
;
Chou, CL
An IVC (Inter-vehicle communication) network is a type of mobile ad hoc networks (MANET) in which high-speed vehicles send, receive, and forward packets via other vehicles on the roads. An IVC network can provide useful applications in future Intelligent Transportation Systems. However, due to frequent network topology changes, a routing path in an IVC network breaks easily. As such, a routing protocol proposed for general MANET (e.g., AODV) performs poorly in IVC networks. To address this problem, we designed and implemented an intelligent flooding-based routing protocol and conducted several field trials to evaluate its performance on the roads. Results obtained from field trials show that (1) our protocol outperforms AODV significantly on IVC networks, and (2) our protocol can make many useful services such as email, ftp, web, video conferencing, and video broadcasting applicable on IVC networks for vehicle users.
A preliminary report on the Phase-I ATSC field test results in Taiwan
(2000)
Tsai, JF
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Lin, CC
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Hang, HM
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Tarng, JH
;
Yu, HC
In May 1998, Taiwan formally adopted the ATSC Digital Television (DTV) as its local digital terrestrial broadcasting standard. In order to define the DTV service area and specify the transmission parameters, we like to know the characteristics of the DTV signal over the local irregular terrain, the impact of interference, and the relationship between the signal power and video quality. me measured the DTV signal and compared the DTV and the NTSC service availability. We selected 100 test sites in Taipei city and its vicinity including three types of environment: urban, suburban and rural areas. In general, the DTV system has a clear advantage over the NTSC system in reception quality.
A volume rendering algorithm using an analytic approach for curvilinear volumes
(1999-11-01)
Lin, CC
;
Ching, YT
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資訊工程學系
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Department of Computer Science
A new approach is presented to visualize curvilinear volume data produced using the CFD or FEM Methods. Ray, casting methods are effective and renders images with good quality. However, these methods suffer from a tremendous number of computations and can not deal with the curvilinear volume efficiently. The marching cubes method is a popular approach when the ambiguity problem reduces the reliability of the rendered image. We propose a new method to solve these problems. Our method is a cell-by-cell process which constructs sosurfaces using trilinear functions. Several speed up techniques are proposed to reduce the number of computations in our algorithm. In addition to this, error analysis and error minimization are also discussed. Our method is also easy to implement parallelized.
Activation of the calcineurin-nuclear factor of activated T-cell signal transduction pathway in atrial fibrillation
(2003-10-28)
Lai, LP
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Lin, CC
;
Lin, JL
;
Lin, CS
;
生物科技學系