Browsing by Author "Lin, Chang-Hsien"

Now showing 1 - 8 of 8

A Numerical Study of Si-TMD Contact with n/p Type Operation and Interface Barrier Reduction for Sub-5 nm Monolayer MoS2 FET
(2016-01-01)
Tang, Ying-Tsan
;
Li, Kai-Shin
;
Li, Lain-Jong
;
Li, Ming-Yang
;
Lin, Chang-Hsien
An atomic-scale numerical study of Si contact with transition metal dichalcogenides (TMD) semiconductor materials is proposed by first-principles simulation for the first time. The monolayer MoS2 channel can be operated as both of n- and p-type FET by properly doping Si S/D to adjust the TMD channel potential. The gradient MoSx junction of dichalcogenide vacancies enables Si-MoS2 contact resistance lower than 100 Omega-mu m for interface Schottky barrier height reduction. The compact Si-MoS2 interface study can potentially provide monolayer TMD contact design guideline for the sub-5 nm TMD FET fabrication technology.
Estimating the Detection Stability of a Si Nanowire Sensor Using an Additional Charging Electrode
(2013)
Chen, Min-Cheng
;
Chen, Hsiao-Chien
;
Lee, Ta-Hsien
;
Lin, Yu-Hsien
;
Shih, Jyun-Hung
This paper proposes a sensing stability estimation method that involves using an additional forcing electrode to simulate the surface charge coupling effect for bottom gate nanowire sensors. The alteration of the Si nanowire can be observed by using the charging electrode without any complex surface treatment and micro-channel setup. The nanowire sensor has a distinct charge-sensitive slope (V-th shift > 60 mV/10(-16)C) with a wire-width scaling of 35 nm. The proposed estimation technique simplifies the charge sensing operation.
First Fully Functionalized Monolithic 3D(+) IoT Chip with 0.5 V Light-electricity Power Management, 6.8 GHz Wireless-communication VCO, and 4-layer Vertical ReRAM
(2016-01-01)
Hsueh, Fu-Kuo
;
Shen, Chang-Hong
;
Shieh, Jia-Min
;
Li, Kai-Shin
;
Chen, Hsiu-Chih
For the first time, we report low-cost heterogeneously integrated sub-40nm epi-like Si monolithic internet of thins (IoT) 3D(+)-IC with wireless communication, light-electricity power management and vertical ReRAM (VRRAM) modules. High current driving multi-channel 3D(+) UTB-MOSFETs (600 mu A/282 mu A@V-G = +/- 1V for 10-channel P/N FETs) was fabricated by low thermal budget super-CMP-planarized visible laser-crystallized epi-like Si channel and CO2 far-infrared laser annealing (CO2-FIR-LA) activation technologies that support a 6.8GHz high frequency VCO circuits, 0.5V low-voltage power management circuit and drives 20nm 4-layer VRRAM (Set/Reset <1.2V/1.8V, 3-bits/cell). This unique TSV-free monolithic 3D(+)IC process provides the superiority in 3D hetero-integration; we successfully integrate these circuits in a low cost, small footprint, fully functionalized 3D(+) IoT chip.
Hybrid Si/TMD 2D Electronic Double Channels Fabricated Using Solid CVD Few-Layer-MoS2 Stacking for V-th Matching and CMOS-Compatible 3DFETs
(2014)
Chen, Min-Cheng
;
Lin, Chia-Yi
;
Li, Kai-Hsin
;
Li, Lain-Jong
;
Chen, Chang-Hsiao
Stackable 3DFETs such as FinFET using hybrid Si/MoS 2 channels were developed using a fully CMOS-compatible process. Adding several molecular layers (3-16 layers) of the transition-metal dichalcogenide (TMD), MoS2 to Si fin and nanowire resulted in improved (+25%) I-on,I-n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device V-th are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics.
MOS2 U-shape MOSFET with 10 nm Channel Length and Poly-Si Source/Drain Serving as Seed for Full Wafer CVD MOS2 Availability
(2016)
Li, Kai-Shin
;
Wu, Bo-Wei
;
Li, Lain-Jong
;
Li, Ming-Yang
;
Cheng, Chia-Chin Kevin
A U-shape MOS2 pMOSFET with 10nm channel and poly-Si source/drain is demonstrated. The fabrication process is simple. Because the Si S/D serves as the nucleation seed for CVD MOS2 deposition, thin MOS2 is well deposited in the channel region any where over the fully scale oxide coated Si wafer. This is a big step forward toward a low cost multi-layer stacked TMD IC technology.
Random Telegraph Noise in 1X-nm CMOS Silicide Contacts and a Method to Extract Trap Density
(2012-04-01)
Chen, Min-Cheng
;
Lin, Chia-Yi
;
Chen, Bo-Yuan
;
Lin, Chang-Hsien
;
Huang, Guo-Wei
The behavior of random telegraph noise was affected by nickel silicide barrier height engineering in advanced nano-CMOS technologies. Contact resistance fluctuations with magnitude of up to 40% were observed when a Schottky barrier was reduced to 0.2 eV. The large contact resistance instability is attributed to the barrier modification by positive charge trapping and detrapping in a Schottky contact. The prevalence and magnitude of the noise are dependent on the contact area, trap density, trap energy, and the silicide Schottky barrier height. In this letter, we propose a fast method to extract the density of responsible contact traps.
Silicide Barrier Engineering Induced Random Telegraph Noise in 1Xnm CMOS Contacts
(2011)
Chen, Min-Cheng
;
Lin, Chia-Yi
;
Chen, Bo-Yuan
;
Lin, Chang-Hsien
;
Huang, Guo-Wei
For the first time, new random telegraph noise behaviors are reported for silicide band gap engineering in advanced nano CMOS technology. Noise current pulses of up to 40% magnitude are observed when Schottky barrier is reduced to 0.2eV. The large contact resistance instability is attributed to barrier modification at Schottky contact interface by positive charge trapping. The prevalence and magnitude of the noise are dependent on the contact size, trap density, trap energy and the silicide Schottky barrier height. In this work, we report a fast monitor methodology to identify the silicide process induced traps in small silicide contacts for 1Xnm CMOS technology.
TMD FinFET with 4 nm Thin Body and Back Gate Control for Future Low Power Technology
(2015)
Chen, Min-Cheng
;
Li, Kai-Shin
;
Li, Lain-Jong
;
Lu, Ang-Yu
;
Li, Ming-Yang
A 4 nm thin transition-metal dichalcogenide (TMD) body FinFET with back gate control is proposed and demonstrated for the first time. The TMD FinFET channel is deposited by CVD. Hydrogen plasma treatment of TMD is employed to lower the series resistance for the first time. The 2 nm thin back gate oxide enables 0.5 V of Vth shift with 1.2 V change in back bias for correcting device variations and dynamically configuring a device as a high performance or low leakage device. TMD can potentially provide sub-nm thin monolayer body needed for 2 nm node FinFET.