Browsing by Author "Lin, Chang-Tzu"

Now showing 1 - 7 of 7

A New Methodology for Noise Sensor Placement Based on Association Rule Mining
(2016-01-01)
Hung, Yu-Hsiang
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Fang, Sheng-Hsin
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Chen, Hung-Ming
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Chen, Shen-Min
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Lin, Chang-Tzu
Due to near-threshold computing nowadays, voltage emergency is threatening our design margins very seriously. Noise sensors are inserted in order to prevent various integrity issues from happening during runtime. In this work, we use a new technique based on association rule mining to plan and place noise sensors. This new methodology can consider the miss rate (the probability of any node occurring voltage emergency without any detection by placed sensors) and simultaneously minimize the number of sensors utilized. The results show that our approach is very effective in converging the miss rate to zero by the least number of sensors. Compared with the state-of-the-art, we can reduce the number of sensors by half in benchmarks while the miss rate is comparable or even smaller than the prior work.
Effective Power Network Prototyping via Statistical-Based Clustering and Sequential Linear Programming
(2013-01-01)
Liu, Sean Shih-Ying
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Lee, Chieh-Jui
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Huang, Chuan-Chia
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Chen, Hung-Ming
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Lin, Chang-Tzu
In this paper, we propose a framework that automatically generates a power network based on given placed design and verifies the power network by the commercial tool without IR and Electro-Migration (EM) violations. Our framework integrates synthesis, optimization and analysis of power network. A deterministic method is proposed to decide number and location of power stripes based on clustering analysis. After an initial power network is synthesized, we propose a sensitivity matrix G(s) which is the correlation between updates in stripe resistance and nodal voltage. An optimization scheme based on Sequential Linear Programming (SLP) is applied to iteratively adjust power network to satisfy a given IR drop constraint. The proposed framework constantly updates voltage distribution in response to incremental change in power network. To accurately capture voltage distribution on a given chip, our power network models every existing power stripes and via resistances on each layer. Experimental result demonstrates that our power network analysis can accurately capture voltage distribution on a given chip and effectively minimize power network area. The proposed methodology is experimented on two real designs in TSMC 90nm and UMC 90nm technology respectively and achieves 9%-32% reduction in power network area, compared with the results from modern commercial PG synthesizer.
Heterogeneous Chip Power Delivery Modeling and Co-Synthesis for Practical 3DIC Realization
(2017-01-01)
Liao, Wei-Hsun
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Lin, Chang-Tzu
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Fang, Sheng-Hsin
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Huang, Chien-Chia
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Chen, Hung-Ming
Three dimensional IC (3DIC) is becoming practical in today's consumer electronics designs. However, one major problem remains in design synthesis and flow: how to model heterogeneous die(s) with major logic die for power synthesis and signoff. This work provides a realistic model and principle for heterogeneous dies power network for 3DICs. It is based on given abstract or early stage information like bump location and power consumption from the provider. Our work also uses this model to synthesize power network with bottom logic die in the design flow. The result is DRC clean power network without IR and EM violation for all power domains. First, we analyze the location and power consumption of power bump for heterogeneous die(s). Second, according to previous analysis, we decide the stripe location and power sink location of heterogeneous dies model by a clustering method. After the initial model is synthesized, we convert it to a node graph with corresponding resistance of via and metal layer, also nodal voltages. Third, the model is optimized by using Sequential Linear Programming (SLP) to adjust stripe width. It will improve the model iteratively until the target IR-Drop is met. Furthermore, our work will create a pseudo DEF of the proposed model to be incorporated with the commercial tool for verification. We experiment on a real case from design house containing a 3D DRAM stack to demonstrate the effectiveness of this cross-layer realization. Results show that we can save 34% metal layer usage in one of the power domains in our case by using proposed methodology.
Hierarchical Power Network Synthesis for Multiple Power Domain Designs
(2012)
Lee, Chieh-Jui
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Liu, Sean Shih-Ying
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Huang, Chuan-Chia
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Chen, Hung-Ming
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Lin, Chang-Tzu
In this paper, we propose a methodology that synthesize and optimize the power network for design with multiple power domains. An architecture is presented to represent the power network with presence of sleep transistors. The power network is numerically modeled to RC network using Modified Nodal Analysis and solved using Conjugate Gradient Method. Regarding to IR drop effect mitigation, an optimization technique is proposed based on Simulated Annealing that minimize total power stripe area while satisfying a given IR drop constraint. In consideration of multiple power domains, the given power domains are represented in tree-like structure and our algorithm is recursively applied to synthesize and optimize the power network for each power domain in a hierarchical fashion. The proposed methodology is integrated to commercial design tool and experimented on real design case for evaluation. To ensure practical aspect of our approach, evaluation is performed on latest digital design commercial tool. Design data and parameters are extracted using Open Access. The result of our algorithm is fed back to latest commercial tool for final IR and EM analysis. Our algorithm is tested on both industrial testcase and academic MCNC benchmark. Comparing to conventional P/G network, using our power network synthesis can achieve 31% - 35% reduction in total P/G area while satisfying maximum 10% IR-drop constraint.
I-LUTSim: An Iterative Look-Up Table Based Thermal Simulator for 3-D ICs
(2013-01-01)
Pan, Chi-Wen
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Lee, Yu-Min
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Huang, Pei-Yu
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Yang, Chi-Ping
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Lin, Chang-Tzu
This work presents an iterative look-up table based thermal simulator, I-LUTSim, to efficiently estimate the temperature profile of three-dimensional integrated circuits. I-LUTSim includes two stages. First, the pre-process stage constructs thermal impulse response tables. Then, the simulation stage iteratively calculates the temperature profile via the table lookup. With this two-stage scheme, the maximum absolute error of I-LUTSim is less than 0.41% compared with that of a commercial tool ANSYS. Moreover, I-LUTSim is at least an order of magnitude faster than a fast matrix solver SuperLU [1] for the full-chip temperature simulation.
Improving Power Delivery Network Design by Practical Methodologies
(2014-01-01)
Huang, Chia-Chi
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Lin, Chang-Tzu
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Liao, Wei-Syun
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Lee, Chieh-Jui
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Chen, Hung-Ming
There are many works on the power network design and prototyping for digital designs, however some usual and practical design concerns are not addressed. In this work, we present a realistic power network design methodology without IR violation certified by state-of-the-art commercial tool. Our work integrates analysis, optimization and synthesis of power network. In particular, we consider thermal effect and power pad\'s positions during the prototyping of power network. A scenario in placement regarding the violation of design rules is considered and resolved by maximum flow algorithm at the same stage. After the synthesis of initial power network, we generate a sensitivity matrix which is correlated with nodal voltage and resistances of net and via in metal layers. Furthermore, a Sequential Linear Programming(SLP) will be applied to adjust the sensitivity matrix iteratively until the IR drop constraint is satisfied. Our work is experimented on a real design in TSMC 65nm LP process, and the result validates our framework that the IR-Drop can be reduced to 2% of supply voltage.
More Effective Power Network Prototyping by Analytical and Centroid Learning
(2019-01-01)
Chuang, Yu-Hsiang
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Lin, Chang-Tzu
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Chen, Hung-Ming
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Lee, Chi-Han
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Chen, Ting-Sheng
Recently a prior work has been proposed to improve the power distribution network (PDN) design with some practical methodologies. However, we found that such approach will cause redundant resources, resulting in the waste of the metal application. In this paper, we present a more effective design flow to automatically generate a PDN verified by the commercial tool without IR-Drop violation. We propose an analytical model and consider the different types of macros to determine the total metal width of PDN. Moreover, the optimization is based on a centroid learning method from unsupervised learning to consolidate PDN. Our work has experimented on real designs in 65 nm process, 0.18 um generic process, and 40 nm process. The results show that our framework can satisfy the given IR-Drop constraints and simultaneously save lots of metal resource (means no overdesign).