Browsing by Author "Lin, Chao-Ting"

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Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiOx/Si Substrates Using Area-Selective CVD Technology
(2019-12-01)
Chung, Yun-Yan
;
Lu, Kuan-Cheng
;
Cheng, Chao-Ching
;
Li, Ming-Yang
;
Lin, Chao-Ting
For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have successfully grown continuous and uniform WS2 film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the transmission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS2 channels on SiOx/Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 10(6), a subthreshold swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL).
Experimentally Determining the Top and Edge Contact Resistivities of Two-Step Sulfurization Nb-Doped MoS2 Films Using the Transmission Line Measurement
(2019-10-01)
Chung, Yun-Yan
;
Li, Chi-Feng
;
Lin, Chao-Ting
;
Ho, Yen-Teng
;
Chien, Chao-Hsin
This study determined the top (vertical) and edge (horizontal) resistivities of metal-MoS2 contact based on the experimental results obtained using the transmission line measurement structure. A novel two-step sulfurization scheme was conducted for forming Nb-doped MoS2 films on a sapphire substrate. The edge contact resistivity, rho(C_edge), was almost two orders of magnitude lower than the top contact resistivity, rho(C_top). Our findings highlight a simple and effective method to accurately determine the edge and top contact resistances of a metal-two-dimensional material contact.
First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrate
(2019-01-01)
Cheng, Chao-Ching
;
Chung, Yun-Yan
;
Li, Ming-Yang
;
Lin, Chao-Ting
;
Li, Chi-Feng
Area-selective channel material growth for 2D transistors is more desirable for volume manufacturing than exfoliation or wet/dry transfer after large area growth. We demonstrate the first top-gate WS(2)p-channel field-effect transistors (p-FETs) fabricated on SiOx/Si substrate using channel area-selective CVD growth. Smooth and uniform WS2 comprising approximately 6 layers was formed by area-selective CVD growth in which a patterned tungsten-source/drain served as the seed for WS2 growth. For a 40 nm gate length transistor, the device has impressive electrical characteristics: on/off ratio of similar to 10(6), a S.S. of similar to 97 mV/dec.. and nearly zero DIBL.
Use of Ultrafast Time-Resolved Spectroscopy to Demonstrate the Effect of Annealing on the Performance of P3HT:PCBM Solar Cells
(2015-03-04)
Wang, Yu-Ting
;
Chen, Mei-Hsin
;
Lin, Chao-Ting
;
Fang, Jian-Jhih
;
Chang, Che-Jui
The organic solar cells of heterojunction system, ITO/PEDOT:PSS/P3HT:PCBM/Al, with a thermal annealing after deposition of Al exhibit better performance than those with an annealing process before deposition of Al. In this study, ultrafast time-resolved spectroscopy is employed to reveal the underlying mechanism of annealing effects on the performance of P3HT:PCBM solar cell devices. The analyses of all decomposed relaxation processes show that the postannealed devices exhibit an increase in charge transfer, in the number of separated polarons and a reduction in the amount of recombination between excited carriers. Moreover, the longer lifetime for the excited carriers in postannealed devices indicates it is more likely to be dissociated into photocarriers and result in a larger value for photocurrent, which demonstrates the physical mechanism for increased device performance.