Browsing by Author "Lin, Cheng-Yen"

Now showing 1 - 2 of 2

Dark channel prior based video dehazing algorithm with sky preservation and its embedded system realization for ADAS applications
(2019-04-29)
Tsai, Chia-Chi
;
Lin, Cheng-Yen
;
Guo, Jiun-In
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Dark Channel Prior (DCP) is one of the significant dehazing methods based upon the observation of the key features of the haze-free images. But it has disadvantages; high computational complexity, over-enhancement in the sky region, flickering artefacts in video processing, and poor dehazing. Therefore, we propose improved solutions to solve the aforementioned drawbacks. First, we adopt the fast one-dimensional filter, look-up table, and program optimization to reduce the computational complexity. Next, we follow by using a part of the guided filter for sky detection and to preserve the sky region from noise by avoiding over recovery. Then, we propose an airtight update strategy and adjust the radius of a guided filter to reduce the flickering artifacts and also propose an airtight estimation method to produce the better dehazing result as the final step of our algorithm. The improved results from our proposed algorithm are stable and are obtained from the real-time processing suitable for ADAS, surveillance, and monitoring systems. The implementation of the proposed algorithm has yielded a processing speed of 75 fps and 23 fps respectively on an NVIDIA Jetson TX1 embedded platform and Renesas R-Car M2. both on DI (720x480) resolution videos. (C) 2019 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
Optimized Memory Access Support for Data Layout Conversion on Heterogeneous Multi-core Systems
(2014-01-01)
Hsu, Chia-Chen
;
Lin, Cheng-Yen
;
Chen, Shin Kai
;
Liu, Chih-Wei
;
Lee, Jenq-Kuen
Heterogeneous multi-core systems that contain multiple CPUs and GPUs are gaining momentum, as they are providing different computation power to meet the performance demand of modern applications. On such systems, developers try to fully utilize the computation power both for CPU and GPU by using the emerging programming models such as CUDA and OpenCL. To achieve the maximal performance, developers must carefully offload the appropriate workload to the compute devices according to the characteristics of target architecture. Under such scenario, seamlessly data motion between different processors become crucial. Additionally, re-organizing the data layout to fit the target architectures, such as array-of-structure (AOS) for CPU, structure-of-array (SOA) for GPU, and coordinate (COO) format to ELLPACK (ELL) for sparse computation, address such concern. In this paper, we propose a hardware memory manager, which efficiently optimizes the conversion of data layouts for heterogeneous multi-core systems on-the-fly. We address coalescing and sparse format conversion issue in our design. A novel ping-pong transpose architecture is devised to reorganize non-coalescing access pattern, and a histogram unit and sparse address generator are presented to process sparse storage format transformation. Our design reduces the overhead of data transfer and layout transformation among CPU and GPU. In our experiment, our design achieves 68.5 to 2.19 times speed up comparing to software-based library depending on data size.