Browsing by Author "Lin, Chia-Chun"

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A 242mW, 10mm(2) 1080p H.264/AVC high profile encoder chip
(2008)
Lin, Yu-Kun
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Li, De-Wei
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Lin, Chia-Chun
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Kuo, Tzu-Yun
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Wu, Sian-Jin
A 1080p high profile H.264 encoder is designed by the robust reusable silicon IP methodology and fabricated in a 0.13 mu m CMOS technology with an area of 10 mm(2) and 242mW at 145MHz. Compared to the state-of-the-art design targeted at 720p baseline, this design reduces 53.4% power and 46.7% area through parallelism enhanced throughput and cross stage sharing pipeline.
A fast algorithm and its architecture for motion estimation in MPEG-4 AVC/H.264 video coding
(2006)
Lin, Chia-Chun
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Lin, Yu-Kun
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The paper presents a hardware friendly fast algorithm and its architecture for motion estimation (ME) in H.264 video coding. The fast algorithm adopts the quarter pel subsampling and mode filtering that reduces the computing complexity of integer ME by 75%, and only two modes instead of various modes are refined for fractional ME. This also can save about 80% fractional ME cycle counts in average. The simulation result shows that it only increases the bit rate within 2% and at most 0.14dB quality degradation. Finally, the resulted parallel architecture only costs 58% of area cost and requires 48% of cycle counts when compared with the previous designs.
A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video
(2008-07-01)
Lin, Yu-Kun
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Lin, Chia-Chun
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Kuo, Tzu-Yun
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
Motion estimation (ME) in high-definition H.264 video coding presents a significant design challenge for memory bandwidth, latency, and cost because of its large search range and various modes. To conquer this problem, this paper presents a low-latency and hardware-efficient ME design with three design techniques. The first technique on integer-pel ME (IME) adopts parallel instead of serial multiresolution search so that we can process 1080 p @ 60 fps videos with +/- 128 search range within just 256 cycles, 5.95-KB buffers, and 213.7K gates. The second technique on fractional-pel ME (FME) uses a single-iteration six-point search to reduce the cycle count by half with similar gate count and negligible quality loss. The third technique applies a mode-filtering approach to further reduce the bandwidth and cycles and share the buffer of IME and FME. The final ME implementation with 0.13-mu m process can support processing of 1080 p @ 60 fps with just 128.8 MHz, 282.6 K gates, and 8.54-KB buffer, which saves 60% gate count, and 68.9% SRAM buffers when compared with the previous design.
Hardware efficient skip mode detection for H.264/AVC
(2008)
Lin, Chia-Chun
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Lin, Yu-Kun
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The paper presents a low cost skip detection algorithm and its architecture by detecting 4x4-zero block numbers in a macroblock (MB). With this simple detection mechanism and an adaptive threshold; the proposed algorithm can correctly pre-skip 82.62% of total MB encoding, and save up to 82.8% encoding: time and corresponding computing power whereas maintains similar video quality because of the high accuracy prediction. Moreover, the design only occupies 0.63K gate counts so that it can be easily combined with the H.264 encoder implementation without overhead for low power and low complexity.
PMRME: A parallel multi-resolution motion estimation algorithm and architecture for HDTV sized H.264 video coding
(2007)
Lin, Chia-Chun
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Lin, Yu-Kun
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The paper presents a hardware-efficient fast algorithm and its architecture for large search range motion estimation (ME) used in HDTV sized H.264 video coding. To solve the high cost and latency in large search range case, the proposed algorithm processes ME in parallel multi-resolution levels instead of serial process in the previous approach. This enables high data reuse for lower bandwidth and low memory cost. Further combining with our previous proposed mode filtering and bit truncation, the algorithm only increases the bit rate within -0.58% and 3.06% and at most 0.04dB and 0.07dB PSNR degradation for 720p and 1080p sequences respectively. The hardware implementation can save up to 49.5% of area cost and 65% of memory cost compared to the previous approach for large search range to [-128, 127].