Browsing by Author "Lin, Chia-Lung"

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A (50,2,4) Nonbinary LDPC Convolutional Code Decoder Chip over GF(256) in 90nm CMOS
(2012)
Lin, Chia-Lung
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電機學院
A memory-based (m(s) = 50, d(v) = 2, d(c) = 4) nonbinary LDPC convolutional code (NB-LDPC-CC) decoder over GF(256) with layered scheduling is presented. The proposed architecture-aware construction features fewer memory banks, low degree, low period, and better performance. To the best of our knowledge, this is the first architecture discussion and implementation for NB-LDPC-CC decoders. We optimized the architecture of message first-in-first-out (M-FIFO), check node unit, and variable node unit in terms of area and throughput. Jointly designing code and architecture, overall normalized area efficiency can be enhanced by more then six times with respect to decoders of nonbinary LDPC block codes (NB-LDPC BCs). After fabricated in 90nm CMOS, our prototype NB-LDPC-CC decoder chip can achieve maximum throughput of 22.8Mbps with frequency of 285MHz. The measured average power is 211mW at a typical operating voltage of 1.0V.
A 7.72 Gb/s LDPC-CC Decoder with Overlapped Architecture for Pre-5G Wireless Communications
(2016-01-01)
Lin, Chia-Lung
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Liu, Rong-Jie
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Lee, Chen-Yi
LDPC block codes (LDPC-BCs) have attracted great interests in recent years by highly parallel computation and good bit-error-rate performance, and one of the decoder implementation issues is high routing complexity. LDPC convolutional codes (LDPC-CCs) not only release routing complexity but also are natural to dynamic length of data frame. Thus, the codes are very suitable for video stream and pre-5G wireless communication systems. LDPC-CC decoder is composed of several concatenated processors, where the long FIFOs are usually the bottleneck of area and decoding latency. To improve hardware efficiency, we use overlapped architecture to share partial FIFO between processors. Furthermore, check node unit and hybrid-partitioned FIFO are proposed to increase throughput and pipeline efficiency. The measurement results of test chip in 65nm technology show that our work can achieves 7.72 Gb/s under 322MHz operating frequency. The decoder with 6 processors occupies an area of 1.19 mm(2), drawing 410.5 mW of power with an energy efficiency of 8.75pJ/bit/proc.
An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm
(2016-09)
Lin, Chia-Lung
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Tu, Shu-Wen
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Lee, Chen-Yi
Nonbinary low-density-parity-check (NB-LDPC) codes, an extension of binary LDPC codes, provide stronger error-correcting capability than binary LDPC codes. However, the performance gain comes together with extraordinary increase on decoding complexity and memory requirement. Many simplification algorithms have been proposed in the literature, and the extended min-sum (EMS) algorithm is the one with minimal performance loss. In this brief, we present an efficient decoder architecture for quasi-cyclic NB-LDPC codes with the EMS algorithm. The throughput is improved by not only the double-throughput elementary check node unit but also overlapped processing for both check node and variable node units (VNUs). To reduce memory usage and computing complexity, edge-message hiding and simplified VNU are proposed as well. With these schemes, the postlayout results of a decoder for a (112, 56) NB-LDPC over GF(64) are presented. The core area occupies 2.24mm(2) and consumes 274 mW with a throughput of 124.6 Mb/s. Compared to prior NB-LDPC decoders with a similar code rate, the proposed decoder achieves better hardware efficiency and energy efficiency.
Heterogeneous nuclear ribonucleoprotein M associates with mTORC2 and regulates muscle differentiation
(2017-01-20)
Chen, Wei-Yen
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Lin, Chia-Lung
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Chuang, Jen-Hua
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Chiu, Fu-Yu
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Sun, Yun-Ya
Mammalian target of rapamycin (mTOR) plays a range of crucial roles in cell survival, growth, proliferation, metabolism, and morphology. However, mTOR forms two distinct complexes, mTOR complex 1 and mTOR complex 2 (mTORC1 and mTORC2), via association with a series of different components; this allows the complexes to execute their wide range of functions. This study explores further the composition of the mTORC2 complex. Utilizing Rictor knock-out cells, immunoprecipitation and mass spectrometry, a novel Rictor associated protein, heterogeneous nuclear ribonucleoprotein M (hnRNP M), was identified. The association between hnRNP M and Rictor was verified using recombinant and endogenous protein and the binding site was found to be within aa 1 similar to 532 of hnRNP M. The presence of hnRNP M significantly affects phosphorylation of SGK1 S422, but not of Akt S473, PKC alpha S657 and PKC zeta T560. Furthermore, hnRNP M also plays a critical role in muscle differentiation because knock-down of either hnRNP M or Rictor in C2C12 myoblasts reduced differentiation. This decrease is able to be rescued by overexpression SGK S422D in hnRNP M knockdown C2C12 myoblasts. Taken together, we have identified a novel Rictor/mTOR binding molecule, hnRNP M, that allows mTORC2 signaling to phosphorylate SGK1 thus regulating muscle differentiation.
Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture
(2015-10-01)
Lin, Chia-Lung
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電子工程學系及電子研究所
In this paper, a design approach for architecture-aware nonbinary low-density parity-check convolutional codes (NB-LDPC-CCs) is presented to jointly optimizes the code performance and decoder complexity for achieving high energy-efficiency decoder. The proposed NB-LDPC-CCs not only feature simple structure and low degree, but also compete with other published NB-LDPC-CCs on error-correction capability. With these codes, we present a memory-based layered decoder architecture, where the computation units and the scheduling of the computations are optimized to increase energy efficiency. To demonstrate the feasibility of proposed techniques, a time-varying (50,2,4) NB-LDPC-CC over GF(256) is constructed, and associated decoder is implemented in 90 nm CMOS. The code can reach BER = 10(-5) at SNR = 0.9 dB, and support multi code rates with puncturing. Comparing with the state-of-the-art designs, the proposed decoder can save 74% power under the same number of iterations, making it suitable for emerging Internet of Things (IoT) applications.