Browsing by Author "Lin, Chia-Pin"

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Fixed-dose combination of amlodipine and atorvastatin improves clinical outcomes in patients with concomitant hypertension and dyslipidemia
(1970-01-01)
Lin, Chia-Pin
;
Tung, Ying-Chang
;
Hsiao, Fu-Chih
;
Yang, Chia-Hung
;
Kao, Yi-Wei
Hypertension and dyslipidemia are important risk factors for cardiovascular disease. However, the clinical outcomes of fixed-dose combination (FDC) versus free-equivalent combination (FEC) of amlodipine and atorvastatin in the treatment of concurrent hypertension and dyslipidemia remain unknown. In this study, we included patients with newly diagnosed hypertension and dyslipidemia, without previously established cardiovascular disease, and treated with either FDC or FEC of amlodipine and atorvastatin were identified from the National Health Insurance Research Database of Taiwan and follow-up for 5 years. By using 1:1 propensity score matching, a total of 1756 patients were enrolled in this study. The composite of major adverse cardiovascular events, including all-cause mortality, myocardial infarction (MI), stroke, and coronary revascularization, occurred more frequently in the FEC group than in the FDC group (hazard ratio, 1.88; 95% confidence interval [CI], 1.42 to 2.5). Although the all-cause mortality did not differ (hazard ratio, 0.46; 95% CI, 0.36 to 1.59), the FEC group developed increased MI, stroke, and coronary revascularization (hazard ratio, 2.87; 95% CI, 1.07 to 7.68; hazard ratio, 1.97; 95% CI, 1.41 to 2.74; and hazard ratio, 2.44; 95% CI, 1.26 to 4.69, respectively). Furthermore, as an unexpected result, a higher risk to develop new-onset diabetes mellitus was observed with FEC regimens (hazard ratio, 2.19; 95% CI, 1.6 to 3.0). In conclusion, although the all-cause mortality did not differ between the two groups, the FDC regimen of amlodipine and atorvastatin improved clinical outcomes when compared to FEC in patients with newly diagnosed hypertension and dyslipidemia.
Fully-depleted SOI MOSFET device and process for fabricating the same
(2006-11-16)
Tsui, Bing-Yue
;
Lin, Chia-Pin
The present invention proposes a nano-scale high-performance SOI MOSFET device and a process for manufacturing the same. The device is characterized by comprising: a metal oxide semiconductor, formed on the SOI substrate; a silicide layer (05), wherein a gate consists of a single full silicide gate (10), a high-K dielectric layer (08) and a part for work function modification (09); and source/drain (6) are complete through a silicide reaction and has a modified Schottky junction.
Impact of back gate bias on hot-carrier effects of n-channel tri-gate FETs (TGFETs)
(2006)
Lin, Chia-Pin
;
Tsui, Bing-Yue
;
電機學院
;
電子工程學系及電子研究所
;
College of Electrical and Computer Engineering
The hot-carrier effects of non-planar tri-gate SOI FET (TGFET) with back-gate bias were investigated. Negative back gate bias could raise the influence of buried oxide defects and then degrade the device quickly. For TGFETs with ultra-narrow fin width and side gate extension, the smaller buried oxide interface area and more obvious screening effect terminate the field lines to obviate the back gate bias efficiently. The extrapolated hot-carrier lifetime encourages the TGFETs as promising sub-10nm devices.
Low threshold voltage CMOSFETs with NiSi fully silicided gate and Modified Schottky barrier source/drain junction
(2007)
Lin, Chia-Pin
;
Tsui, Bing-Yue
;
Hsieh, Chih-Ming
;
Huang, Chih-Feng
;
電子工程學系及電子研究所
Low threshold voltage CMOSFETs with NiSi fully silicided gate and Modified Schottky barrier source/drain junction were fabricated. Symmetric threshold voltage was obtained by implant-to-silicide technique. Lateral growth rate and thermal stability of NiSi on SiO2 were investigated. Single silicide and low temperature process make the proposed process very promising in sub-45nm technology nodes.
Process and characteristics of fully silicided source/drain (FSD) thin-film transistors
(2006-12-01)
Lin, Chia-Pin
;
Hsiao, Yi-Hsuan
;
Tsui, Bing-Yue
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, high-performance fully silicided source/drain (FSD) thin-film transistors (TFTs) with FSD and ultrashort source/drain extension (SDE) fabricated by the implantto-silicide (ITS) technique are studied thoroughly. Using the ITS technique, not only the implantation damage but also the silicide spiking is avoided so that the thermal budget can be decreased obviously. The offstate current (I-off) of the FSD TFTs is equal to (n-channel) or smaller than (p-channel) that of the conventional TFTs. At onstate, due to the FSD and the SDE structure, the parasitic resistance of the S/D region and the carrier-injection resistance between silicide and channel are reduced. Therefore, superior onstate/offstate current ratio can be obtained. The influences of annealing temperature and time are also examined in this paper. A 600 degrees C/30-s rapid thermal annealing is sufficient to diffuse and activate dopants and, then, fabricate high-performance FSD TFTs. Excellent short-channel behavior of the FSD TFT is also confirmed. To conclude, the high-performance FSD TFT with low parasitic resistance fabricated by low-thermal-budget process is very promising for active-matrix liquid-crystal display, active-matrix organic light-emitting-diode display, and system-on-panel applications.